音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CXK77L18R160GB Datasheet

  • CXK77L18R160GB

  • MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-High-Speed Sy...

  • 235.26KB

  • 22頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

SONY
廬
Description
CXK77L18R160GB
3/33/4
Preliminary
16Mb LW R-R HSTL High Speed Synchronous SRAM (1M x 18)
The CXK77L18R160GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words
by 18 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer
onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, pro-
viding a high-performance user interface.
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K
(Input Clock).
During read operations, output data is driven valid from the rising edge of K, one full clock cycle the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle the address is registered.
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching
resistor RQ. By connecting RQ between ZQ and V
SS
, the output impedance of all DQ pins can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 333 MHz operation is obtained from a single
1.8V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
鈥?/div>
3 Speed Bins
-3
-33
-4
Cycle Time / Access Time
3.0ns / 1.5ns
3.3ns / 1.7ns
4.0ns / 2.0ns
鈥?Single 1.8V power supply (V
DD
): 1.8V
鹵
0.1V
鈥?Dedicated output supply voltage (V
DDQ
): 1.5V
鹵
0.1V
鈥?HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): 0.75V typical
鈥?Register - Register (R-R) read operations
鈥?Late Write (LW)
鈥?Full read/write coherency
鈥?Byte Write capability
鈥?Differential input clocks (K/K)
鈥?Asynchronous output enable (G)
鈥?Programmable impedance output drivers
鈥?Sleep (power down) mode via dedicated mode pin (ZZ)
鈥?JTAG boundary scan (subset of IEEE standard 1149.1)
鈥?119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb LW R-R, rev 1.0
1 / 22
June 3, 2002

CXK77L18R160GB相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！