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CXK77L18162GB Datasheet

  • CXK77L18162GB

  • MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SR...

  • 23頁

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SONY
廬
Description
CXK77L18162GB
25/27/3
Preliminary
16Mb DDR1 HSTL High Speed Synchronous SRAM (1M x 18)
The CXK77L18162GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words
by 18 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a two-deep write buffer
onto a single monolithic IC. Single Data Rate (SDR) and Double Data Rate (DDR) Register - Register (R-R) Read operations
and Late Write (LW) Write operations are supported, providing a flexible, high-performance user interface. Continue operations
are supported, providing burst capability. Positive and negative output clocks are provided for applications requiring source-
synchronous operation.
All address and control input signals except the G output enable signal are registered on the rising edge of the CK differential
input clock. All commands are input via the B(1:3) control signals.
During SDR read operations, output data is driven valid once, from the rising edge of CK, one full clock cycle after the address
is registered. During DDR read operations, output data is driven valid twice, first from the rising edge of CK and then from the
falling edge of CK, beginning one full clock cycle after the address is registered. In both cases, output data transitions are closely
aligned with output clock transitions.
During SDR write operations, input data is registered once, on the rising edge of CK, one full clock cycle after the address is
registered. During DDR write operations, input data is registered twice, first on the rising edge of CK and then on the falling
edge of CK, beginning one full clock cycle after the address is registered.
Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external
control resistor RQ between ZQ and V
SS
, the impedance of all data and clock output drivers can be precisely controlled.
400 MHz operation (800 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using
a subset of IEEE standard 1149.1 protocol.
Features
鈥?/div>
3 Speed Bins
-25
-27
-3
Cycle Time / Access Time
2.5ns / 1.8ns
2.7ns / 1.9ns
3.0ns / 1.9ns
Data Rate
800 Mbps
740 Mbps
666 Mbps
鈥?Single 1.8V power supply (V
DD
): 1.8V
鹵
0.1V
鈥?Dedicated output supply voltage (V
DDQ
): 1.5V to 1.8V typical
鈥?HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): V
DDQ
/2 typical
鈥?DDR1 functional compatibility
鈥?Register - Register (R-R) read protocol
鈥?Late Write (LW) write protocol
鈥?Single Data Rate (SDR) and Double Data Rate (DDR) data transfers
鈥?Burst capability via Continue commands
鈥?Linear or interleaved burst order, selectable via dedicated mode pin (LBO)
鈥?Full read/write coherency
鈥?Two cycle deselect
鈥?Differential input clocks (CK/CK)
鈥?Positive and negative output clocks (CQ/CQ) - one pair per 18 bits of output data (DQ)
鈥?Asynchronous output enable (G)
鈥?Programmable output driver impedance
鈥?JTAG boundary scan (subset of IEEE standard 1149.1)
鈥?153 pin (9x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb DDR1, rev 1.3
1 / 23
July 19, 2002

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