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CXD8302Q Datasheet

  • CXD8302Q

  • PLL for CCD Cameras

  • 10頁

  • SONY   SONY

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CXD8302Q
PLL for CCD Cameras
For the availability of this product, please contact the sales office.
Description
The CXD8302Q has the functions needs to
configure a PLL circuit with a timing generator and
external sync signals for a CCD of 480K pixels (EIA,
effective pixels) and 570K pixels (CCIR, effective
pixels).
Features
鈥?/div>
EIA and CCIR compatible
鈥?/div>
Compatible with component digital and composite
digital recording format
鈥?/div>
Both SYNC and VD/HD signals can be used for
external sync signals
Absolute Maximum Ratings
鈥?/div>
Supply voltage
V
DD
V
SS
鈥?0.3 to +7
V
鈥?/div>
Input voltage
V
I
V
SS
鈥?0.3 to V
DD
+0.3 V
鈥?/div>
Storage temperature Tstg
鈥?0 to +125
擄C
Recommended Operating Conditions
鈥?/div>
Supply voltage
V
DD
4.5 to 5.5
鈥?/div>
Operating temperature Topr
0 to 70
Block Diagram
f
H
f
V
V reset
19
EXTf
H
44 pin QFP (Plastic)
Applications
CCD cameras
Structure
Silicon gate CMOS IC
V
擄C
EXTSYNC
EXTHD
EXTVD
15
14
13
Separation
of f
H
and f
V
65 Clocks
Delay
V latch
MODE1
MODE2
26
31
Pulse Generation Circuit
Frequency Division
EIA : 1/572
(1/568)
CCIR: 1/576
(1/567)
2f
H
H timing
20
41
42
43
44
INTf
H
HD
VD
SYNC
BLK
Latch
EIA/CCIR
32
Frequency Division
EIA : 1/525
CCIR: 1/625
V timing
CLKI
38
8
2
3
4
7
8
9 10 11
37
CLKO
INTf
H
phase setting
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
E94320A52-PP

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