音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CXD3204R Datasheet

  • CXD3204R

  • IEEE1394 LSI for D-STB, D-VHS, and DTV

  • 2頁

  • SONY   SONY

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

CXD3204R
IEEE1394 LSI for D-STB, D-VHS, and DTV
Description
The CXD3204R is an LSI integrating Link Layer and
Physical Layer conforming to the IEEE1394-1995 serial
bus standard on a single chip.
Link Layer provides MPEG2 t ra nsp or t stre am
dedicated input interface and output interface, IEC958
audio stream I/O interface and output interface for D/A
c o nve r t e r a s a d a t a i n t e r fa c e fo i s o c h r o n o u s
communication. Also, a maximum 512 bytes of
asynchronous communication is possible.
Physical Layer provides two poarts for 1394 cable
i n t e r fa c e , a n d s u p p o r t s t r a n s fe r s p e e d o f
200/100Mbit/s. Also, this layer provides received packet
data regeneration repeat function, arbitration function
and bus initialization logic.
T h i s L S I u t i l i ze s A p p l e C o m p u t e r 鈥檚 F i r e W i r e
technology.
176-pin LQFP (Plastic)
Feature Summary
Conforms to IEEE1394-1995 serial bus standard
Supports 100Mbps/200Mbps
Link layer
x
Supports DVB transport streams
x
Supports IEC958 audio stream
x
Built-in PID 鏗乴ter function
x
2-channel isochronous simultaneous
transmission/synchronous transmission and
reception
x
Supports DMA (2-channel) transfer using host
bus
x
Isochronous data inserted from asynchronous
data port
x
Built-in cipher circuit conforming to DTCP format
x
Large capacity FIFO
Isochronous Transmit/Receive FIFO:
960 x 32-bit x 2
Asynchronous Transmit FIFO: 132 x 33-bit
Asynchronous Receive FIFO: 133 x 33-bit
x
CIP header automatic attachment/detection
Physical layer
x
Live wire detection function when port is
connected to operation node
x
Automatic shutdown function against stopport for
powersaving
x
Bus initialization and arbitration state machine
logic
x
Re-synchronization for reception data for local
clock
x
Link-On packet recognition
x
DS link encode/decode
x
196.603MHz PLL
EL
IM
IN
A
Application
x
Cable power reduction is detected with cable
power status
x
Supports con鏗乬uration manager cable and power
class de鏗乶ition pin.
x
Independent 2-port TpBias
Digital interface for D-STB, D-VHS and DTV
Absolute Max. Ratings
(T
A
= 25
o
C, V
SS
= 0V)
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
DD
V
I
V
O
T
OPR
T
STG
V
SS
-0.5 ~ +4.6
V
SS
-0.5 ~ V
DD
+0.5
V
SS
-0.5 ~ V
DD
+0.5
-20 ~ +75
-55 ~ +150
V
V
V
o
C
o
C
Recommended Operating Conditions
V
DD
3.0 ~ 3.6
Supply voltage
Operating temperature
T
OPR
-20 ~ +75
V
o
C
PR
Revision 0.0 (5/22/99)
R
Y
1

CXD3204R相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP,
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù):
賣家服務(wù):
技術(shù)客服:

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號,
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人:

聯(lián)系方式:

按住滑塊,拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見,您的參與是維庫提升服務(wù)的動力!意見一經(jīng)采納,將有感恩紅包奉上哦!