CXD2951GA-2
Single Chip GPS LSI
Description
The CXD2951GA-2 is a dedicated single chip LSI
for the GPS (Global Positioning System), satellite-
based location measurement system. This LSI
enables the configuration of a single chip system
providing a cost-effective, low-power solution.
Compared with conventional methods, position
detection time and sensitivity are substantially
improved with the use of an advanced signal
processing scheme. With the integration of both the
Radio and baseband blocks into a single CMOS IC,
the CXD2951GA-2 is ideal for use in automotive,
cellular handset, handheld navigation, mobile
computing and other location-based applications.
Features
鈥?/div>
12-channel GPS receiver capable of simultaneously
receiving 12 satellites
鈥?/div>
Reception frequency: 1575.42MHz
(L1 band, CA code)
鈥?/div>
Reference clock (TCXO) frequency:
18.414MHz (GPS, Sony standard),
The unique frequency of major applications is available,
such as GSM and W-CDMA. (optional)
13.000MHz (GSM),
14.400MHz (CDMA),
16.368MHz (GPS),
19.800MHz (PDC/CDMA),
26.000MHz (GSM)
176 pin LFLGA (Plastic)
Radio
鈥?/div>
Image Rejection Mixer
鈥?/div>
VCO Tank
鈥?/div>
IF Filters
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
鈥?/div>
Supply voltage I/O
IOV
DD
鈥?/div>
Supply voltage core
CV
DD
鈥?/div>
Supply voltage radio V
DD
鈥?/div>
Input voltage
V
I
鈥?/div>
Output voltage
V
O
鈥?/div>
Operating temperature Topr
鈥?/div>
Storage temperature Tstg
鈥?.5 to +4.6
鈥?.5 to +2.5
鈥?.5 to +2.5
鈥?.5 to +6
鈥?.5 to +6
鈥?0 to +85
鈥?0 to +150
V
V
V
V
V
擄C
擄C
鈥?/div>
32 bits RISC CPU (ARM7TDMI)
鈥?/div>
288K-bytes Program ROM
鈥?/div>
72K-bytes Data RAM
Power is supplied only to 8K-byte Data RAM while
in backup mode.
鈥?/div>
System power management
鈥?/div>
1-channel UART
鈥?/div>
Internal RTC (Real Time Clock)
鈥?/div>
10-bit successive approximation system A/D
converter, A/D data available on NMEA messages
鈥?/div>
All-in-view positioning
鈥?/div>
Communication format: Supports NMEA-0183
鈥?/div>
1 PPS output
鈥?/div>
Supports assisted-GPS for cellular (optional)
Recommended Operating Conditions
鈥?/div>
Supply voltage I/O
IOV
DD
3.0 to 3.6
V
鈭?/div>
Under operation with internal ROM, using no
external expansion bus:
IOV
DD
2.6 to 3.6
V
鈭?/div>
Under operation in backup mode:
BKUPIOV
DD
2.5 (Min.) V
鈥?/div>
Supply voltage core
CV
DD
1.62 to 1.98
V
鈥?/div>
Supply voltage radio V
DD
1.62 to 1.98
V
鈥?/div>
Operating temperature Topr
鈥?0 to +85
擄C
Input/Output Pin Capacitance (Baseband)
鈥?/div>
Input capacitance
C
IN
9 (Max.)
鈥?/div>
Output capacitance
C
OUT
11 (Max.)
鈥?/div>
I/O capacitance
C
I/O
11 (Max.)
pF
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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