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CXD2510Q Datasheet

  • CXD2510Q

  • CD Digital Signal Processor

  • 710.77KB

  • 48頁

  • SONY   SONY

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CXD2510Q
CD Digital Signal Processor
Description
The CXD2510Q is a digital signal processor LSI for
CD players and is equipped with the following functions.
鈥?Wide frame jitter margin (鹵28 frames) due to a built-
in 32K RAM
鈥?Bit clock, which strobes the EFM signal, is
generated by the digital PLL
鈥?EFM data demodulation
鈥?Enhanced EFM frame sync signal protection
鈥?Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
鈥?Quadruple-speed, double-speed and variable pitch
playback
鈥?Noise reduction during track jumps
鈥?Auto zero-cross mute
鈥?Subcode demodulation and Sub Q data error
correction
鈥?Digital spindle servo (built-in oversampling filter)
鈥?16-bit traverse counter
鈥?Asymmetry compensation circuit
鈥?Serial bus-based CPU interface
鈥?Error correction monitor signals are output from a
new CPU interface.
鈥?Servo auto sequencer
鈥?Fine search which performs high-precision track
jumps
鈥?Digital audio interface output
鈥?Digital level meter, peak meter
鈥?Bilingual compatible
Features
鈥?All digital signals processed with a single chip
during playback
鈥?High-integrated mounting possible due to a built-in
RAM
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
V
DD
鈥?/div>
Supply voltage
鈥?.3 to +7.0 V
鈥?/div>
Input voltage
V
I
鈥?.3 to +7.0 V
(V
SS
鈥?0.3V to V
DD
+ 0.3V)
鈥?/div>
Output voltage
V
O
鈥?.3 to +7.0 V
鈥?/div>
Storage temperature Tstg
鈥?0 to +125 擄C
鈥?/div>
Supply voltage difference
Vss 鈥?AVss 鈥?.3 to +0.3 V
V
DD
鈥?AV
DD
鈥?.3 to +0.3 V
80 pin QFP (Plastic)
-L051
-L01
Recommended Operating Conditions
4.50 to 5.50
V
鈥?/div>
Supply voltage
V
DD
鈭?/div>
鈥?/div>
Operating temperature Topr
鈥?0 to +75
擄C
鈭?/div>
The V
DD
(min.) for the CXD2510Q varies according
to the playback speed and built-in VCO selection.
The V
DD
(min.) is 4.50 V when high speed VCO
and quadruple-speed playback are selected
(variable pitch off). The V
DD
(min.) for the
CXD2510Q under various conditions are as shown
in the following table.
V
DD
(min.) [V]
Playback
speed
VCO high-speed VCO normal-speed
脳
4
脳
2
鈭?/div>
1
脳
2
脳
1
脳
1
鈭?/div>
2
4.50
4.00
3.40
3.40
3.40
鈥?/div>
鈥?/div>
4.00
3.40
3.40
Dashes indicate that there is no assurance of the
processor operating. All values are for variable pitch off.
鈭?/div>
1
When the internal operation of the LSI is set to
normal-speed playback and the operating clock
of the signal processor is doubled, double-speed
playback results.
鈭?/div>
2
When the internal operation of the LSI is set to
double-speed mode and the crystal oscillating
frequency is halved in low power consumption
mode, normal-speed playback results.
Input/output Capacitances
鈥?/div>
Input capacitance
C
I
鈥?/div>
Output capacitance C
O
Note)
Measurement conditions
12 (max.)
pF
12 (max.)
pF
for high impedance
V
DD
= V
I
= 0V
f
M
= 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
E94412A11

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