CXD2422R
CCD Camera Timing Generator
Description
The CXD2422R generates the timing pulses
required for driving and signal processing CCDs with
480,000 pixels (EIA, effective pixels) and CCDs with
570,000 pixels (CCIR, effective pixels).
Features
鈥?/div>
EIA and CCIR compatible
鈥?/div>
Compatible with component digital and composite
digital recording format
鈥?/div>
Compatible with field/frame accumulation modes
Applications
CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX062/063AL
64 pin LQFP (Plastic)
Absolute Maximum Ratings
鈥?/div>
Supply voltage
V
DD
V
SS
鈥?0.5 to +7.0
V
鈥?/div>
Input voltage
V
I
V
SS
鈥?0.5 to V
DD
+ 0.5 V
鈥?/div>
Output voltage
V
O
V
SS
鈥?0.5 to V
DD
+ 0.5 V
鈥?/div>
Operating temperature
Topr
鈥?0 to +75
擄C
鈥?/div>
Storage temperature
Tstg
鈥?5 to +150
擄C
Recommended Operating Conditions
鈥?/div>
Supply voltage
V
DD
4.5 to 5.5
鈥?/div>
Operating temperature
Topr
鈥?0 to +75
V
擄C
Block Diagram
SDO
D1
D2
D3
VD
5
51 1
SD 30
SC 31
LD 32
9
Shift
Register
13
Latch
4
2
3
4
HD
6
39
XSG1
D0
V latch
38 XSG2
44 XV1
43 XV2
Shutter data
HTSG 58
FLD/FRM 61
EIA/CCIR 62
MODE 63
Reset
High-speed
Pulse
Generation
Circuit
42 XV3
Output
F.F.
41
XV4
Latch
Pulse Generation Circuit
35 XSUB
26 HCLP1
22 HCLP2
21 VCLP
XH gate
Internal clock
CLKI 33
28 PBLK
Delay
Delay
27 PBLKON
34
14 15 16
18 19 20
54 53 52
37 36
7
CLKO
SHP
XRG
BCO
BAO
SHD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
BBO
鈥?鈥?/div>
XH1
XH2
CLK
BAI
BBI
BCI
E94Y30-ST
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