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CXD1958Q Datasheet

  • CXD1958Q

  • MMDS TCM/QAM Demodulator + FEC + ADC

  • 331.11KB

  • 48頁

  • SONY   SONY

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CXD1958Q
MMDS TCM/QAM Demodulator + FEC + ADC
Description
The CXD1958Q is an integrated TCM/QAM
demodulator for MMDS systems using the DAVIC
MMDS standard. This highly integrated device
incorporates an internal 8-bit ADC, image rejection
and root-raised cosine filters, all-digital symbol timing
recovery PLL, adaptive decision feedback equalizer
(DFE) with 10 feedforward and 30 feedback taps, 4-D
TCM decoder, and DAVIC/DVB compliant forward
error correction comprising (204,188) Reed Solomon
decoder, a programmable de-interleaver with I = 12
and I = 204, and a de-randomiser. All internal clocks
are generated from a single external 30MHz reference
crystal.
Device functionality also includes 3-wire bus interface
for configuring up to 2 tuner synthesizers, a sigma
delta tuner IF-AGC output, a user programmable RF-
AFC sigma delta output, spectrum inversion of the
received signal for tuner compatibility, and a highly
configurable MPEG2-TS interface. An I
2
C bus
interface provides on-board configuration and status
monitoring of various functions including access to
the equalizer tap values and constellation points.
JTAG provides boundary scan test compatibility.
Features
鈥?/div>
DAVIC MMDS V1.1 and V1.3 compliant
鈥?/div>
Supports 16, 64 and 256QAM
鈥?/div>
Supports 16, 64 and 256 TCM
鈥?/div>
Internal 8-bit ADC
鈥?/div>
Interface for 10-bit external ADC
鈥?/div>
36.125MHz nominal IF input
鈥?/div>
Symbol rate range 5 鈥?5.304Mbaud in 6MHz
channels
鈥?/div>
Integrated matched filtering with 0.15 roll-off factor
鈥?/div>
鹵400KHz internal carrier offset compensation with
negligible losses @ 5Mbaud 6MHz channel
鈥?/div>
Symbol timing loop designed to acquire with large
offsets. Negligible losses for 鹵100ppm offsets
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Preliminary
100 pin QFP (Plastic)
鈥?/div>
All internal clocks derived from single fixed
frequency crystal (30MHz)
鈥?/div>
Supports fast re-acquisition mode
鈥?/div>
6碌s echo cancellation @ 5Mbaud
鈥?/div>
Constellation points and equalizer tap values
readable via I
2
C bus
鈥?/div>
C/N estimation readable via I
2
C bus
鈥?/div>
Low implementation loss for AWGN only:
0.5dB @ 64QAM (using internal 8-bit A/D);
0.3dB @ 256QAM (excluding A/D);
measured at BER of 3x10
鈥?
Pre R/S
鈥?/div>
I = 12 and I = 204 de-interleaving
鈥?/div>
Fast I
2
C bus compatible control interface
鈥?/div>
Tuner IF-AGC output
鈥?/div>
User programmable tuner RF-AGC output
鈥?/div>
Dedicated 3-wire bus interface to configure up to 2
tuner synthesizers
鈥?/div>
3.3V CMOS technology
鈥?/div>
Supports JTAG boundary scan
鈥?/div>
100-pin QFP package
Applications
MMDS set-top boxes
鈥?鈥?/div>
PE99906-PS

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