鈥?/div>
Allowable power dissipation
P
D
4.2
0 to +85
鈥?5 to +150
333
V
擄C
擄C
mW
Block Diagram and Pin Configuration
SDATAN
GNDA
GNDT
REXT
V
CC
A
V
DD
Recommended Operating Condition
Supply voltage
3.3 鹵 0.3
SDATAP
CKPOL
LPFB
LPFA
GND
CE
V
36 35 34 33 32 31 30 29 28 27 26 25
GND
37
REFREQ
38
CNTL
39
DE
40
SFTCLK
41
HSYNC
42
VSYNC
43
B7
44
B6
45
B5
46
B4
47
V
DD
48
Encoder
P/S
Converter
PLL
Cable
Driver
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
GND
1
GND
2
B3
3
B2
4
B1
5
B0
6
G7
7
G6
8
G5
9 10 11 12
G4
G3
G2
V
DD
Fig. 1. Block Diagram and Pin Configuration
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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