鈥?/div>
Allowable power dissipation
P
D
Operating Condition
Supply voltage
7
鈥?5 to +85
鈥?5 to +150
300
V
擄C
擄C
mW
Vcc
2.7 to 5.5
V
Block Diagram and Pin Configuration
OSCI
1
20
蠁R
NC
2
Phase
Comparator
19
NC
OSCO
3
18
蠁P
Vp
4
Reference Programmable
Counter 14bits
17
TEST
V
CC
5
16
D
O
2
D
O
1
6
Charge
Pump 1
Charge
Pump 2
15
FC
GND
7
14
LAT
LD
8
Pulse Swallow
Counter 7bits
Programmable
Counter 11bits
13
DATA
NC
9
1-bit Latch 14-bit Latch
18-bit Shift Resister
1-bit Shift
Resister
12
PS
FIN
10
2-modulus
prescaler
1
1
or
64/65
128/129
Pulse swallow programmable counter
11
CK
18-bit Latch
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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