鈥?/div>
Allowable power dissipation
V
CC
DV
CC
Topr
4.0 to 10.0
3.5 to V
CC
鈥?0 to +75
V
V
擄C
Block Diagram and Pin Configuration
OUT2
(VARIABLE)
13
10
OUT1
(VARIABLE)
10kHz
LINE
OUT2
OUT2
(FIX)
DV
CC
1kHz
4kHz
DC2
IN2
V
CC
22
21
20
19
18
17
14dB
16
15
14
12
29dB
VOLUME
GRAPHIC EQUALIZER
CONTROL
GRAPHIC EQUALIZER
BIAS
14dB
29dB
VOLUME
1
400Hz
2
100Hz
3
BAL
4
VOL
5
DC1
6
1N1
7
GND
8
LINE
OUT1
9
OUT1
(Fix)
11
ISET
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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