鈥?/div>
GPS receivers
analog and digital signals for CDMA and GPS operation. For a
given operation, the CX20536 accepts analog In-phase (I) and
Quadrature (Q) signals, performs channel selection low-pass
filtering, and converts the analog baseband signals into digital
signals. For clock generation, the CX20536 includes internal
digital and Phase Locked Loop (PLL) clock synthesis for 19.2,
19.68, and 19.8 MHz system clocks. It also provides the
capability to accept the CHIPx8 clock from the Mobile Station
Modem (MSM) or equivalent baseband device. The CX20536 also
integrates a VHF PLL synthesizer to synthesize a receive
Intermediate Frequency (IF) Local Oscillator (LO).
The CX20536 operates within a power supply voltage range of 2.7
V to 3.3 V. Power control logic maintains a minimum power
consumption. Electrical performance parameters are designed to
operate over the 鈥?0
擄C
to +85
擄C
range. The device is available
in a 32-pin, 5 x 5 x 1 mm RF Land Grid Array (RFLGA) package.
The device package and pinout are shown in Figure 1. A system
block diagram of the CX20536 is shown in Figure 2.
Features
鈥?/div>
Single supply voltage 2.7 to 3.3 V
鈥?/div>
Operational temperature 鈥?0
擄C
to +85
擄C
鈥?/div>
Low power consumption in all operating modes including sleep
operation
鈥?/div>
Single mode for CDMA phones, but also with GPS position
location capability
鈥?/div>
Receive signal path includes:
鈭?/div>
Separate CDMA, GPS filters, and ADCs
鈭?/div>
DC offset correction
鈥?/div>
Receive VHF PLL synthesizer:
鈭?/div>
Programmable charge pump current
鈭?/div>
Lock detector output
鈭?/div>
Operate in conjunction with CDMA/GPS mode receive
functions
鈥?/div>
System clock generation:
鈭?/div>
19.2, 19.68, and 19.8 MHz system clock support
鈭?/div>
CHIPx8 accepts external CHIPx8 clock (9.8304 MHz or
8.184 MHz)
鈥?/div>
Mode control logic for receive/GPS and sleep modes
鈥?/div>
Functionality similar to the CX20489 and CX20529, with GPS
processing capability
鈥?/div>
RFLGA鈩?(32-pin, 5 x 5 x 1 mm) package
AVDD_RX
IOFFSET
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
QOFFSET
RXQ鈥?/div>
RXQ+
RXI+
RXI鈥?/div>
AVDD_SYN
AVSS_SYN
RXPDOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RXQD1
VREFN
VREFP
RBIAS
VC
RXQD2
RXQD3
RXQD4
RXID1
RXID2
RXID3
RXID4
SLEEP
SYN_ENA
Description
The CX20536 is a receive-only Code Division Multiple Access
(CDMA) and Global Positioning System (GPS) Baseband Analog
Processor (BAP) for dual-mode CDMA and GPS-capable portable
phones. The device is designed to interface between the receive
section and the digital processing circuitry of the telephone.
The CX20536 includes all of the circuitry needed to support
receive baseband signal processing and conversions between
RXPLL_IN
CHIPX8IN
SYN_DATA
SYN_CLK
PLLFLTR
DVDD
TCXO
LOCK
C1387
Figure 1. CX20536 Pinout 鈥?32-Pin RFLGA
(Top View)
Skyworks Solutions, Inc. 鈥?Phone [781] 376-3000 鈥?Fax [781] 376-3100 鈥?sales@skyworksinc.com 鈥?www.skyworksinc.com
103089B 鈥?Skyworks Proprietary and Confidential information 鈥?Products and Product Information are Subject to Change Without Notice 鈥?January 14, 2005
1
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