鈥?/div>
Dual-band, dual-mode mobile phones
DESCRIPTION
The CX20489 is a receive-only Baseband Analog Processor
(BAP) that can be used for Code Division Multiple Access
(CDMA) and Advanced Mobile Phone System (AMPS)
Frequency Modulation (FM) baseband signals. The device is
designed for dual-mode CDMA and AMPS portable phones.
The CX20489 is designed to interface between the Radio
Frequency (RF) receive section and the digital processing
circuitry of the telephone. The device includes all of the
circuitry needed to support the receive baseband signal
processing and conversions between analog and digital signals
for CDMA and AMPS (FM).
For a given operation, the CX20489 accepts analog baseband
In-phase (I) and Quadrature-phase (Q) signals, performs
channel selection low-pass filtering, and converts the analog
baseband signals into digital signals. For clock generation, the
CX20489 includes internal digital and Phase-Locked Loop
(PLL) clock synthesis for 19.2, 19.68, and 19.8 MHz system
clocks. The device also provides the capability to generate or
to accept the CHIPx8 clock to or from the Mobile Station
Modem (MSM) or equivalent baseband device. The CX20489
also integrates a VHF PLL synthesizer to synthesize the receive
Intermediate Frequency (IF).
The CX20489 is characterized for operation from a power
supply voltage range of 2.7 V to 3.3 V, with power control logic
to maintain a minimum power consumption. Electrical
performance parameters are designed to operate over the
鈥?0
擄C
to +85
擄C
range. The device is available in 40-pin
6 x 6 mm RF Land Grid Array (RFLGA鈩? package.
A system block diagram of the CX20489 is shown in Figure 1.
FEATURES
鈥?/div>
Single supply voltage from 2.7 to 3.3 V
鈥?/div>
Operational temperature of 鈥?0
擄C
to +85
擄C
鈥?/div>
Low power consumption in all operating modes including
sleep operation
鈥?/div>
Dual mode for CDMA and FM operation
鈥?/div>
Receive signal path includes:
鈭?/div>
Separate CDMA/FM filters and ADCs
鈭?/div>
DC offset control loop
鈥?/div>
Receive VHF PLL synthesizer:
鈭?/div>
Programmable charge pump current
鈭?/div>
Lock detector output
鈥?/div>
System clock generation:
鈭?/div>
19.2, 19.68, and 19.8 MHz system clock support
鈭?/div>
Accepts external CHIPx8 clock (9.8304 MHz or 8.184
MHz) and/or generates an internal CHIPx8 clock
(9.8304 MHz)
鈭?/div>
Adjustable TCXO or TCXO/4 clock output driver levels and
power-down capability
鈭?/div>
Provides a TCXO clock through the TCXO/4 output pin
鈥?/div>
Mode control logic for Rx, sleep, and idle modes
鈥?/div>
Pin-for-pin and functional compatibility with Skyworks鈥?/div>
CX20529 Baseband Analog Processor (but without GPS
processing capability)
鈥?/div>
40-pin 6 x 6 mm RFLGA鈩?package
Skyworks Solutions, Inc., Proprietary and Confidential
103088A
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM M
1
FEBRUARY 5, 2003
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