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CW001103 Datasheet

  • CW001103

  • CW001103 ARM966E-S Microprocessor Core preliminary 10/01

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CW001103
ARM966E-S
Microprocessor Core
Preliminary Datasheet
The CW001103 ARM966E-S core integrates the ARM9E-S 32-bit
processor, an instruction RAM, a data RAM, a write buffer, and an AHB
bus interface. The CW001103 supports both the 32-bit ARM and 16-bit
Thumb instruction sets, allowing you to trade off between high
performance and high code density. Additionally the CW001103 supports
the ARM9E instruction extensions. It provides an enhanced multiplier for
increased DSP performance. The CW001103 core is developed using
LSI Logic鈥檚 G12
廬
-p performance process.
Figure 1
CW001103 Block Diagram
Instruction
SRAM
Dout
Addr
Din
Data
SRAM
Dout
Addr
Din
AHB Bus
Interface Unit
and
Write Buffer
System
Control
Coprocessor
(CP15)
External
Coprocessor
Interface
IA
DA
WDATA
ARM9E-S
Core
INSTR
RDATA
System
Controller
ETM
Interface
DB08-000124-01
October 2001
Rev. B
Copyright 漏 2000, 2001 by LSI Logic Corporation. All rights reserved.
1 of 32

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