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CW000502GIGABLAZE Datasheet

  • CW000502GIGABLAZE

  • CW000502GigaBlaze transceiver cores G11 .25 micron

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GigaBlaze Transceiver Cores
First Gigabit Per Second CMOS Transceiver Cores In The Industry
Overview
LSI Logic鈥檚 GigaBlaze
cores are the first multi-gigabit per second CMOS transceiver
cores in the industry. They provide a full-duplex, point-to-point communications
channel for gigabit speed serial interfaces. Protocol independence enables the
cores to be used with standard high-speed communications protocols to create a
high-speed serial interface. Applications for the cores include storage subsystems,
network switches and routers, System Area Network (SAN) and high-speed
backplanes.
The GigaBlaze cores are optimally designed for use as a physical layer for high-
speed protocols including Fibre Channel, Gigabit Ethernet, and the emerging
System Area Network (SAN) standard. Multiple GigaBlaze cores can be
integrated into a single ASIC. Combined with other LSI Logic standards-based
cores, such as Merlin鈩?Fibre Channel, the TinyRISC鈩?and MiniRISC鈩?/div>
processors, and PCI, the GigaBlaze core enables a completely new approach to
high-performance, single- chip solution for increased differentiation and reduced
chip count, power and cost. The third generation GigaBlaze transceiver is now
available in LSI Logic鈥檚 G11鈩?process technology, along with the G10 and 500K
process technologies.
Description
The GigaBlaze core consists of deserializer and serializer pattern and alignment
circuitry. The deserializer receives a serial gigabit speed input encoded data
stream and converts it into parallel data. This parallel data acts as an input for
any high-speed protocol handler. Likewise, encoded parallel data from the pro-
tocol handler can be transmitted at gigabit speeds after being converted into a ser-
ial stream by the serializer.
The core transmitter serializes the parallel data with clock information
embedded in it. The serialized output is a low-swing differential signal in NRZ
format. The receiver recovers data and the embedded clock from the serial data
stream, performs byte synchronization and presents parallel data with respect to
the recovered clock.
The LSI Logic CoreWare design program provides the complex building blocks,
proven design methodology, technology and application support necessary to build a
system on a chip, optimized uniquely for the target application. This single-chip
approach reduces overall system costs and accelerates time to market.
GigaBlaze G11 Core
The GigaBlaze G11 core is LSI Logic鈥檚 third
generation CMOS serial transceiver core.The
GigaBlaze G11 core transmits data up to 2.5
Gbits/sec.
鈥?/div>
Serial Transfer Rate: 1.0625, 1.25, 2.125
and 2.5 Gbits/sec
鈥?/div>
ASIC Process Technology:
G11, 2.5 V, 0.25-micron, cell-based
CMOS process
鈥?/div>
Parallel Data Interface:
Transmitter and receiver set independently
for either 10 to 20 bits wide

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