CVLD-025 Model
5X7 mm SMD,
2.5V, LVDS
Frequency Range:
Temperature Range:
Storage:
Input Voltage:
Control Voltage:
Input Current:
Output:
Symmetry:
Rise/Fall Time:
Pulling Range:
Linearity:
Logic:
Terminated 100ohms
Temp. 0擄C to 70擄C
50MHz to 200MHz
0擄C to 70擄C
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Differential LVDS
Voltage Controlled
Clock Oscillator
Designed to meet today's
requirements for 2.5V
Differential LVDS applications.
The CVLD-025 provides very
low phase noise & jitter for
demanding applications.
Available on 16mm tape and
reel in quantities of 1,000pcs..
-45擄C to 90擄C
2.5V 鹵 0.125V
1.25V 鹵 1.25V
50mA Typ, 80mA Max
Differential LVDS
40/60% Max @ 50% Vdd
1ns Max
鹵50ppm APR Min. (std)
鹵 10% Max
(Offset 1.25V Typ.)
"0" = 1.10 Typical
"1" = 1.43 Typical
0.5psec Typ., 1psec RMS Max
Jitter:
Aging:
12KHz to 20MHz
<5ppm 1st/yr, <2ppm every year thereafter
Dimensions inches (mm)
All dimensions are Max unless otherwise specified.
.283
(7.20)
SUGGESTED PAD LAYOUT
.055 鹵.003
(1.40 鹵.08)
#1
#2
#5
#3
#4
.040 鹵.003
(1.0 鹵.08)
.148
(3.75)
.071 SQ
(1.80)
P/N
Freq DC
Denotes pad 1
.203
(5.15)
.079
(2.0)
#6
.200 鹵.005
(5.08 鹵.13)
Bottom View
.200
(5.08)
Bypass Capacitor Recommended
RECOMMENDED REFLOW SOLDERING PROFILE
TEMPERATURE
260擄C
217擄C
200擄C
150擄C
Ramp-Up
3擄C/Sec Max.
Critical Temperature
Zone
Ramp-Down
6擄C/Sec.
Crystek Part Number Guide
CVLD-025 - 50 - 155.520
#1
#2
#3
#4
#5
Pulling (APR) Min.
#1 Crystek 5x7 SMD PECL VCXO
#2 Model 025 = 2.5V
#3 Temp. Range: Blank = 0/70擄C
#4 Pulling: (see Table 1)
#5 Frequency in MHz: 3 or 6 decimal places
Blank
50 (std)
鹵 100ppm
鹵 50ppm
Preheat
180 Secs. Max.
8 Minutes Max.
90 Secs. Max.
Table 1
260擄C for
10 Secs. Max.
Example:
CVLD-025-50-155.520 = 2.5V, 40.60, 0/70擄C, 50ppm APR, 155.520 MHz
NOTE: Reflow Profile with 240擄C peak also acceptable.
Pad
1
2
3
4
5
6
Connection
Volt Cont.
E/D
GND
OUT
COUT
Vdd
Enable/Disable Function
E/D pin
Open
"1" level 2.2V Min
"0" level 0.4V Max
Output pin
Active
Active
High Z
Specifications subject to change without notice.
TD-070301 Rev.A
1
