CD74HC374, CD74HCT374,
CD74HC574, CD74HCT574
Data sheet acquired from Harris Semiconductor
SCHS183
February 1998
High Speed CMOS Logic Octal D-Type Flip-Flop,
Three-State Positive-Edge Triggered
Description
The Harris CD74HC374, CD74HCT374, CD74HC574 and
CD74HCT574 are Octal D-Type Flip-Flops with Three-State
Outputs and the capability to drive 15 LSTTL loads. The eight
edge-triggered flip-flops enter data into their registers on the
LOW to HIGH transition of clock (CP). The Output Enable
(OE) controls the three-state outputs and is independent of
the register operation. When Output Enable (OE) is HIGH the
outputs will be in the high impedance state. The 374 and 574
are identical in function and differ only in their pinout
arrangements.
Features
鈥?Buffered Inputs
[ /Title
(CD74
HC374
,
CD74
HCT37
4,
CD74
HC574
,
CD74
HCT57
鈥?Common Three-State Output Enable Control
鈥?Three-State Outputs
鈥?Bus Line Driving Capability
鈥?Typical Propagation Delay (Clock to Q) = 15ns at
V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
Ordering Information
PART NUMBER
CD74HC374E
CD74HCT374E
CD74HCT574E
CD74HC574E
CD74HC574M
CD74HC374M
CD74HCT374M
CD74HCT574M
NOTES:
1. When ordering, use the entire part number. Add the suf鏗亁 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
TEMP. RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
PKG.
NO.
E20.3
E20.3
E20.3
E20.3
M20.3
M20.3
M20.3
M20.3
Pinouts
CD74HC374, CD74HCT374
(PDIP, SOIC)
TOP VIEW
CD74HCT574
(PDIP, SOIC)
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
GND 10
GND 10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1998
File Number
1663.1
1
1
2
3
4
5
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8
9
