Data sheet acquired from Harris Semiconductor
SCHS154
CD74HC161, CD74HCT161,
CD74HC163, CD74HCT163
High Speed CMOS Logic
Presettable Counters
Description
The Harris CD74HC161, CD74HCT161, CD74HC163 and
CD74HCT163 are presettable synchronous counters that
feature look-ahead carry logic for use in high-speed
counting applications. The CD74HC161 and CD74HCT161
are asynchronous reset decade and binary counters,
respectively; the CD74HC163 and CD74HCT163 devices
decade and binary counters, respectively and are reset
synchronously with the clock. Counting and parallel
presetting are both accomplished synchronously with the
negative-to-positive transition of the clock.
A low level on the synchronous parallel enable input, SPE,
disables counting operation and allows data at the P0 to P3
inputs to be loaded into the counter (provided that the
setup and hold requirements for SPE are met).
All counters are reset with a low level on the Master Reset
input, MR. In the CD74HC163 and CD74HCT163 counters
(synchronous reset types), the requirements for setup and
hold time with respect to the clock must be met.
Two count enables, PE and TE, in each counter are
provided for n-bit cascading. In all counters reset action
occurs regardless of the level of the SPE, PE and TE inputs
(and the clock input, CP, in the CD74HC161 and
CD74HCT161 types).
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
The look-ahead carry feature simplifies serial cascading of
the counters. Both count enable inputs (PE and TE) must
be high to count. The TE input is gated with the Q outputs
of all four stages so that at the maximum count the terminal
count (TC) output goes high for one clock period. This TC
pulse is used to enable the next cascaded stage.
February 1998
Features
鈥?CD74HC161, CD74HCT161 4-Bit Binary Counter,
Asynchronous Reset
鈥?CD74HC163, CD74HCT163 4-Bit Binary Counter,
Synchronous Reset
鈥?Synchronous Counting and Loading
鈥?Two Count Enable Inputs for n-Bit Cascading
鈥?Look-Ahead Carry for High-Speed Counting
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
[ /Title
(CD74
HC161
,
CD74
HCT16
1,
CD74
HC163
,
CD74
HCT16
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Preset-
table
Counte
rs,
High
Speed
Ordering Information
PART NUMBER
CD74HC161E
CD74HC161M
CD74HC163E
CD74HC163M
CD74HCT161E
CD74HCT161M
CD74HCT163E
CD74HCT163M
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to ob-
tain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
TEMP. RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld PDIP
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
PKG.
NO.
E16.3
M16.15
E16.3
M16.15
E16.3
M16.15
E16.3
M16.15
Pinout
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
(PDIP, SOIC)
TOP VIEW
MR 1
CP 2
P0 3
P1 4
P2 5
P3 6
PE 7
GND 8
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
9 SPE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1998
File Number
1550.1
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