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CD74HCT138 Datasheet

  • CD74HCT138

  • High Speed CMOS Logic 3-to-8 Line Decoder/Demultiplexer Inve...

  • 14頁

  • TI

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Data sheet acquired from Harris Semiconductor
SCHS147A
CD74HC138, CD74HCT138,
CD74HC238, CD74HCT238
High Speed CMOS Logic 3-to-8 Line Decoder/
Demultiplexer Inverting and Non-Inverting
October 1997 - Revised February 1999
Features
鈥?Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
鈥?l/O Port or Memory Selector
鈥?Three Enable Inputs to Simplify Cascading
鈥?Typical Propagation Delay of 13ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
[ /Title
(CD74
HC138
,
CD74
HCT13
8,
CD74
HC238
,
CD74
HCT23
8)
/Sub-
ject
(High
Speed
Pinout
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
(PDIP, SOIC)
TOP VIEW
A0 1
A1 2
A2 3
E1 4
E2 5
E3 6
(Y7) Y7 7
GND 8
16 V
CC
15 Y0 (Y0)
14 Y1 (Y1)
13 Y2 (Y2)
12 Y3 (Y3)
11 Y4 (Y4)
10 Y5 (Y5)
9 Y6 (Y6)
Signal names in parentheses are for 鈥橦C238 and 鈥橦CT238.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
1999, Texas Instruments Incorporated
1

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