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CD4013BC Datasheet

  • CD4013BC

  • Dual D-Type Flip-Flop

  • fairchild

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CD4013BC Dual D-Type Flip-Flop
October 1987
Revised January 1999
CD4013BC
Dual D-Type Flip-Flop
General Description
The CD4013B dual D-type flip-flop is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent data, set, reset, and clock inputs
and 鈥淨(jìng)鈥?and 鈥淨(jìng)鈥?outputs. These devices can be used for
shift register applications, and by connecting 鈥淨(jìng)鈥?output to
the data input, for counter and toggle applications. The
logic level present at the 鈥淒鈥?input is transferred to the Q
output during the positive-going transition of the clock
pulse. Setting or resetting is independent of the clock and
is accomplished by a high level on the set or reset line
respectively.
Features
s
Wide supply voltage range:
s
High noise immunity:
compatibility:
3.0V to 15V
0.45 V
DD
(typ.)
s
Low power TTL: fan out of 2 driving 74L
or 1 driving 74LS
Applications
鈥?Automotive
鈥?Data terminals
鈥?Instrumentation
鈥?Medical electronics
鈥?Alarm system
鈥?Industrial electronics
鈥?Remote metering
鈥?Computers
Ordering Code:
Order Number
CD4013BCM
CD4013BCSJ
CD4013BCN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150鈥?Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and SOP
Truth Table
CL
(Note 1)
D
0
1
x
x
x
x
R
0
0
0
1
0
1
S
0
0
0
0
1
1
Q
0
1
Q
0
1
1
Q
1
0
Q
1
0
1



x
x
x
No Change
x
=
Don't Care Case
Note 1:
Level Change
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005946.prf
www.fairchildsemi.com

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CD4013BC

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