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CA91 Datasheet

  • CA91

  • CMOS AccelArray

  • 90.75KB

  • 8頁

  • FUJITSU   FUJITSU

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FUJITSU SEMICONDUCTOR
DATA SHEET
DS06-10801-4E
Semicustom
CMOS
AccelArray
TM
CA91 Series
鈻?/div>
DESCRIPTION
AccelArray
TM
* is a new structured ASIC family, offering short development time, and low development cost with
pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers.
By using 0.11
碌m
CMOS process technology, the devices can support 6 million logic gates, 4.55 Mbits SRAM
and 3.125 Gbps high speed transmission macros. Ultra-high pin count FC-BGA (up to 729 pins to 1681 pins)
packages are available.
* : AccelArray
TM
is a trademark of Fujitsu Limited.
鈻?/div>
FEATURES
鈥?High-speed, large scale ASIC produced in short development time:
TAT = One third compared with Standard Cell ASICs (target value)
鈥?Uses an architecture that simplifies physical design tasks.
鈥?Pre-designed common masters with IR-drop free.
鈥?Pre-designed test circuit insertion to reduce test synthesis tasks.
鈥?Uses a dedicated timing-driven layout tool to reduce development time.
鈥?Signal Integrity Free (pre-designed main clock trees without design verifications)
鈥?Max built-in gate number : 6,000,000 gates or more
鈥?Technology : 0.11
碌m
Silicon gate CMOS, 6 to 7-metal layers (wiring material: copper), low-k inter-layer film
鈥?Internal cells support high-speed operation
鈥?Power supply voltage : +1.2 V 鹵 0.1 V/2.5 V
鹵
0.2 V (Dual power supply. Needs 1.5 V power supply during using
HTSL.) .
鈥?Operation junction temperature :
鈭?0 擄C
to
+125 擄C
(standard)
鈥?Max operating frequency: 333 MHz (internal circuit)
鈥?Support for fast interface/macro (200 MHz/400 MHz DDR I/F, 2.5 Gbps PCI Express, 3.125 Gbps XAUI, etc.)
鈥?Special interfaces (P-CML,LVDS,PCI,HSTL,SSTL-2, etc.)
鈥?Embedded macro : PLL, SRAM
鈥?8-channel clock supply system incorporating a PLL
鈥?Supports Memory-BIST/Boundary-SCAN
鈥?Package : FC-BGA (729 pins to 1681 pins)
鈥?ARM core is supported.
Note : It contains under planning.

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