廬
CA3420
Data Sheet
October 4, 2005
FN1320.9
0.5MHz, Low Supply Voltage, Low Input
Current BiMOS Operational Amplifier
The CA3420 is an integrated circuit operational amplifier that
combines PMOS transistors and bipolar transistors on a
single monolithic chip. The CA3420 BiMOS operational
amplifier features gate protected PMOS transistors in the
input circuit to provide very high input impedance, very low
input currents (less than 1pA). The internal bootstrapping
network features a unique guardbanding technique for
reducing the doubling of leakage current for every 10擄C
increase in temperature. The CA3420 operates at total
supply voltages from 2V to 20V either single or dual supply.
This operational amplifier is internally phase compensated to
achieve stable operation in the unity gain follower
configuration. Additionally, it has access terminals for a
supplementary external capacitor if additional frequency roll-
off is desired. Terminals are also provided for use in
applications requiring input offset voltage nulling. The use of
PMOS in the input stage results in common mode input
voltage capability down to 0.45V below the negative supply
terminal, an important attribute for single supply application.
The output stage uses a feedback OTA type amplifier that
can swing essentially from rail-to-rail. The output driving
current of 1.5mA (Min) is provided by using nonlinear current
mirrors.
Features
鈥?2V Supply at 300碌A(chǔ) Supply Current
鈥?1pA Input Current (Typ) (Essentially Constant to 85擄C)
鈥?Rail-to-Rail Output Swing (Drive
鹵2mA
into 1k鈩?Load)
鈥?Pin Compatible with 741 Operational Amplifiers
鈥?Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
鈥?pH Probe Amplifiers
鈥?Picoammeters
鈥?Electrometer (High Z) Instruments
鈥?Portable Equipment
鈥?Inaccessible Field Equipment
鈥?Battery-Dependent Equipment (Medical and Military)
Functional Diagram
X1
Ordering Information
PART
NUMBER
CA3420E
CA3420EZ
(Note)
PART
MARKING
CA3420E
CA3420EZ
TEMP.
RANGE (擄C)
-55 to 125
-55 to 125
PACKAGE
8 Ld PDIP
8 Ld PDIP*
(Pb-free)
PKG.
DWG. #
E8.3
E8.3
X1
-
MOS
BIPOLAR
+
MOS
BIPOLAR
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free plus anneal products employ special
Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant
and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
BUFFER AMPS;
BOOTSTRAPPED
INPUT PROTECTION
NETWORK
HIGH GAIN
(50K)
OTA BUFFER
(X2)
Pinout
CA3420 (PDIP)
TOP VIEW
OFFSET NULL
INV.
INPUT
NON-INV.
INPUT
V-
1
2
3
4
8 STROBE
-
+
7 V+
6 OUTPUT
5 OFFSET NULL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright 漏 Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
INTERSIL
1
2
3
4
5
