廬
November 2002
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PROD E PRODUCT
LETE
I T UT
at
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SUBST port Center
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POSSI
al Sup
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FOR A our Technic ww.intersil.c
t
contac TERSIL or w
IN
1-888-
CA3318
CMOS Video Speed,
8-Bit, Flash A/D Converter
Features
鈥?CMOS Low Power with SOS Speed (Typ) . . . . . . . .150mW
鈥?Parallel Conversion Technique
鈥?15MHz Sampling Rate (Conversion Time) . . . . . . . 67ns
鈥?8-Bit Latched Three-State Output with Overflow Bit
鈥?Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .
鹵1
LSB
鈥?Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V
鈥?2 Units in Series Allow 9-Bit Output
鈥?2 Units in Parallel Allow 30MHz Sampling Rate
Description
The CA3318 is a CMOS parallel (FLASH) analog-to-digital
converter designed for applications demanding both low
power consumption and high speed digitization.
The CA3318 operates over a wide full scale input voltage
range of 4V up to 7.5V with maximum power consumption
depending upon the clock frequency selected. When
operated from a 5V supply at a clock frequency of 15MHz,
the typical power consumption of the CA3318 is 150mW.
The intrinsic high conversion rate makes the CA3318 ideally
suited for digitizing high speed signals. The overflow bit
makes possible the connection of two or more CA3318s in
series to increase the resolution of the conversion system. A
series connection of two CA3318s may be used to produce a
9-bit high speed converter. Operation of two CA3318s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 15MHz to 30MHz).
256 paralleled auto balanced voltage comparators measure
the input voltage with respect to a known reference to
produce the parallel bit outputs in the CA3318.
255 comparators are required to quantize all input voltage
levels in this 8-bit converter, and the additional comparator is
required for the overflow bit.
Applications
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
TV Video Digitizing (Industrial/Security/Broadcast)
High Speed A/D Conversion
Ultrasound Signature Analysis
Transient Signal Analysis
High Energy Physics Research
General-Purpose Hybrid ADCs
Optical Character Recognition
Radar Pulse Analysis
Motion Signature Analysis
碌P
Data Acquisition Systems
Part Number Information
PART NUMBER LINEARITY (INL, DNL)
CA3318CE
CA3318CM
CA3318CD
鹵1.5
LSB
鹵1.5
LSB
鹵1.5
LSB
SAMPLING RATE
15MHz (67ns)
15MHz (67ns)
15MHz (67ns)
TEMP. RANGE (
o
C)
-40 to 85
-40 to 85
-40 to 85
PACKAGE
24 Ld PDIP
24 Ld SOIC
24 Ld SBDIP
PKG. NO.
E24.6
M24.3
D24.6
Pinout
CA3318
(PDIP, SBDIP, SOIC)
TOP VIEW
(LSB) B1 1
B2 2
B3 3
B4 4
B5 5
B6 6
B7 7
(MSB) B8 8
OVERFLOW 9
1
/ R 10
4
24 V
AA
+ (ANA. SUP.)
23
3
/
4
R
22 V
REF
+
21 V
IN
20 p
19 PHASE
18 CLK
17 V
AA
- (ANA. GND)
16 V
IN
15 V
REF
-
14 CE1
13 CE2
(DIG. GND) V
SS
11
(DIG. SUP.) V
DD
12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright 漏 Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
FN3103.3
1
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