S E M I C O N D U C T O R
CA3240, CA3240A
Dual, 4.5MHz, BiMOS Operational Ampli鏗乪r
with MOSFET Input/Bipolar Output
Description
The CA3240A and CA3240 are dual versions of the popular
CA3140 series integrated circuit operational ampli鏗乪rs. They
combine the advantages of MOS and bipolar transistors on the
same monolithic chip. The gate-protected MOSFET (PMOS)
input transistors provide high input impedance and a wide
common-mode input voltage range (typically to 0.5V below the
negative supply rail). The bipolar output transistors allow a wide
output voltage swing and provide a high output current capability.
The CA3240A and CA3240 are compatible with the industry
standard 1458 operational ampli鏗乪rs in similar packages.The off-
set null feature is available only when these types are supplied in
the 14 lead PDIP package (E1 suf鏗亁).
November 1996
Features
鈥?Dual Version of CA3140
鈥?Internally Compensated
鈥?MOSFET Input Stage
- Very High Input Impedance (Z
IN
) 1.5T鈩?(Typ)
- Very Low Input Current (I
I
) 10pA Typ. at
鹵15V
- Wide Common-Mode Input Voltage Range (V
ICR
):
Can Be Swung 0.5V Below Negative Supply Voltage
Rail
鈥?Directly Replaces Industry Type 741 in Most
Applications
Applications
鈥?Ground Referenced Single Ampli鏗乪rs in Automobile
and Portable Instrumentation
鈥?Sample and Hold Ampli鏗乪rs
鈥?Long Duration Timers/Multivibrators (Microseconds-
Minutes-Hours)
鈥?Photocurrent Instrumentation
鈥?Intrusion Alarm System
鈥?Comparators
鈥?Instrumentation Ampli鏗乪rs
鈥?Active Filters
鈥?Function Generators
鈥?Power Supplies
Ordering Information
PART NUMBER
CA3240AE
CA3240AE1
CA3240E
CA3240E1
TEMP.
RANGE (
o
C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PACKAGE
8 Ld PDIP
14 Ld PDIP
8 Ld PDIP
14 Ld PDIP
PKG.
NO.
E8.3
E14.3
E8.3
E14.3
Pinouts
CA3240, CA3240A, (PDIP)
TOP VIEW
OUTPUT (A)
INV.
INPUT (A)
NON-INV.
INPUT (A)
V-
1
2
3
4
8 V+
7 OUTPUT
INV.
6 INPUT (B)
5 NON-INV.
INPUT (B)
Functional Diagram
2mA
4mA
V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
200碌A(chǔ)
+
1.6mA
200碌A(chǔ)
2碌A(chǔ)
2mA
OUT-
PUT
CA3240, CA3240A, (PDIP)
TOP VIEW
INV.
INPUT (A)
NON-INV.
INPUT (A)
OFFSET
NULL (A)
V-
OFFSET
NULL (B)
NON - INV.
INPUT (B)
INV.
INPUT (B)
1
2
3
4
5
6
7
OFFSET
14 NULL (A)
13 V+
鈥?/div>
12 OUTPUT (A)
11 NC
10 OUTPUT (B)
9 V+
鈥?/div>
OFFSET
8
NULL (B)
IN-
PUT
A
鈮?/div>
10
A
鈮?/div>
10,000
A
鈮?/div>
1
-
C
1
12pF
V-
OFFSET NULL
NOTE: Only available with 14 lead DIP (E1 Suf鏗亁).
鈥?/div>
Pins 9 and 13 internally connected through approximately 3鈩?
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1996
File Number
1050.3
3-115
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