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C9950

3.3V, 180-MHz, Multi-Output Clock Driver

Product Features

鈥?/div>

180-MHz Clock Support

Supports PowerPC鈩? Intel

廬

, and RISC Processors

9 Clock Outputs: Frequency Configurable

Oscillator or Crystal Reference Input

Output Disable Control

Spread Spectrum Compatible

Pin Compatible with MPC950

Industrial Temp. Range: 鈥?0擄C to +85擄C

32-Pin TQFP Package

Table 1. Frequency Table

[1]

FB_SEL = 1

SEL

(A:D)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

QA

4x

2x

QB

2x

x

2x

x

QC

(0,1)

2x

x

2x

x

2x

x

2x

x

QD

(0:4)

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

FB_SEL = 1

QA QB

8x

4x

2x

4x

2x

QC

(0,1)

4x

2x

4x

2x

4x

2x

4x

2x

QD

(0:4)

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

Note:

1. x = is the reference input frequency

Block Diagram

SELA

PLL_EN

TCLK

REF_SEL

VCO

200-

480MHz

Pin Configuration

LPF

8/ 16

FB_SEL

SELB

SELC

MR/OE#

4/ 8

QB

4/ 8

QC0

QC1

VDD

FB_SEL

SELA

SELB

SELC

SELD

VSS

XIN

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

XIN

XOUT

OSC

Phase

Detector

2/ 4

QA

REF_SEL

PLL_EN

TCLK

VSS

QA

VDDC

QB

VSS

C9950

9

10

11

12

13

14

15

16

QC0

VDDC

QC1

VSS

QD0

VDDC

QD1

VSS

Power-On Reset

4/ 8

QD0

QD1

SELD

QD2

QD3

QD4

Cypress Semiconductor Corporation

Document #: 38-07072 Rev. *C

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

XOUT

MR/OE#

VDDC

QD4

VSS

QD3

VDDC

QD2

鈥?/div>

CA 95134 鈥?408-943-2600

Revised December 21, 2002

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版本

描述

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3.3V, 180-MHz, Multi-Output Clock Driver

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