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C9801CY Datasheet

  • C9801CY

  • CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC

  • 103.06KB

  • 11頁

  • ETC

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APPROVED PRODUCT
C9801
Low EMI Clock Generator for Pentium盲 II CPU Systems
with Power Management
盲
Product Features
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Supports Intel Pentium盲 II CPU designs.
133 and 100 Mhz CPU clock support
Designed to meet Intel chipset specification
4 CPU clocks with isolated power supply
2 CPU/2 clock with isolated power supply
8 PCI clocks with isolated power supply
3 IOAPIC clocks with isolated power supply
One 48 MHz fixed clock for USB/Super IO with
isolated power supply
4 3V66 clocks with isolated power supply
2 reference clocks with isolated power supply
<175 pS Max. skew among CPU clocks
<500 pS Max. skew among PCI clocks
Power management control of CPU and PCI clocks
56-pin SSOP package
Spread Spectrum EMI reduction mode
Frequency Table
SEL133/100#
0
CPU
100*
PCI
33.3*
33.3*
1
133*
*See complete table on page 3.
Pin Configuration
VSS
REF0
REF1
VDD
XIN
XOUT
VSS
PCI_F
PCI1
VDDP
PCI2
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
12
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDI
IOAPIC2
IOAPIC1
IOAPIC0
VSS
VDDC
CPU_0/2
CPU_1/2
VSS
VDDC
CPU3
CPU2
VSS
VDDC
CPU1
CPU0
VSS
VDD
VSS
PS#
CS#
PD#
SS#
SEL1
SEL0
VDDF
48M
VSS
Block Diagram
VDDF
Xin
Xout
REF
OSC
REF[0:1]
VDDI
IOAPIC[0:2]
VDDC
CPU[0:3]
VSS
PCI4
PCI5
VDDP
PCI6
PCI7
VSS
VSS
3V66_0
3V66_1
VDDA
VSS
3V66_2
3V66_3
VDDA
SEL[0:1]
SEL133/100#
PD#
CS#
PS#
CPU_(0:1)/2
PLL1
VDDP
PCI [1:7], F
VDDA
3V66 [0:3]
VDDF
PLL2
48M
SEL133/100#
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07049 Rev. **
C9801
PCI3
05/03/2001
Page 1 of 11

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  • 英文版
    CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC
    ETC
  • 英文版
    CPU System Clock Generator
    ETC

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