鈥?/div>
1 differential pair and 1 single ended open drain
CPU clocks
6 PCI clocks
2 REF (3.3V) clocks at 14.318 MHz
1 48 MHz (3.3V), and one 24/48 MHz clock
Power Management through PWR_DN#
13 SDRAM clocks for 3 DIMMs
Cypress Spread Spectrum for best EMI reduction
8 Spread Spectrum settings each frequency
48 Pin SSOP Package
SMBus clock control with readback capability
Fine resolution frequency programming via Dial-a-
廬
Frequency Function
Frequency Table
S3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
S2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
S1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
S0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Table 1
CPU
133.3
75
100.2
66.8
79
110
115
120
133.3
83.3
100.2
66.8
124
129
138
143
PCI
33.3
37.5
33.3
33.4
39.5
36.7
38.3
30
33.3
27.7
33.3
33.4
31.0
32.3
34.5
35.8
Spread
Spectrum
+/- .5%
+/- .5%
+/- .5%
+/- .5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Product Description
The C9706 is a main clock synthesizer chip for VIA
VT8371 (KX133) chipset and AMD Athlon (K7) CPU
based systems. This device provides all clocks required
with spread spectrum for EMI reduction.
It also
includes a comprehensive SMBus control interface to
permit individual clock enable, frequency, and spread
controls via system software.
Block Diagram
VDD
REF0/(CPU_STP#)
XIN
XOUT
Pin Configuration
VDD
REF0/(CPU_STP#)
VSS
XIN
XOUT
VDD
PCI0/MODE
PCI1/S1
VSS
PCI2
PCI3
PCI4
PCI5
VDD
SDRAMIN
VSS
SDRAM11
SDRAM10
VDDS
SDRAM9
SDRAM8
VSS
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/S0
VSS
CPU-OD
VSS
CPU#
CPU
VDD
PWR_DN#
SDRAM12
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
SDRAM6
SDRAM7
VDD
48MHz/S2
24_48MHz/S3
OSC
REF1/S0
PWR_DN#
S0
CPU-OD
Stop
Clock
control
CPU
CPU#
VDD
PCI0/MODE
PCI1/S1
PCI2
PCI3
PCI4
PCI5
VDD
48M/S2
/2
PLL1
S3 S2 S1
SDATA
SCLK
I2C
Logic
PLL2
SDRAMIN
24_48M/S3
VDDS
SDRAM(0:12)
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07041 Rev. **
05/02/2001
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