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C9531 Datasheet

  • C9531

  • PCIX I/O System Clock Generator with EMI Control Features

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C9531
PCIX I/O System Clock Generator with EMI Control Features
Features
鈥?Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
鈥?Input clock frequency of 25 MHz to 33 MHz
鈥?Output frequencies of XINx1, XINx2, XINx3 and XINx4
鈥?One output bank of 5 clocks.
鈥?One REF XIN clock output.
鈥?SMBus clock control interface for individual clock
disabling and SSCG control
鈥?Output clock duty cycle is 50% (鹵 5%)
鈥?< 250 ps skew between output clocks within a bank
鈥?Output jitter <175 ps
鈥?Spread Spectrum feature for reduced electromagnetic
interference (EMI)
鈥?OE pin for entire output bank enable control and
testability
鈥?28-pin SSOP and TSSOP packages
Table 1. Test Mode Logic Table
[1]
Input Pins
OE
HIGH
HIGH
HIGH
HIGH
LOW
S1
LOW
LOW
HIGH
HIGH
X
S0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLK
XIN
2 * XIN
3 * XIN
4 * XIN
REF
XIN
XIN
XIN
XIN
Three-state Three-state
Block Diagram
Pin Configuration
REF
1
2
3
4
5
6
28
27
26
25
24
23
SDATA
SCLK
VSS
VDDP
CLK0
CLK1
CLK2
VSS
VDDP
CLK3
CLK4
VDDA
VSS
SSCG#
SSCG#
SSCG
Logic
/N
1
0
CLK0
CLK1
CLK2
CLK3
CLK4
OE
GOOD#
REF
VDD
XIN
XOUT
VSS
S0
S1
GOOD#
VSS
IA0
IA1
IA2
VDDA
OE
C9531
XIN
XOUT
7
8
9
10
11
12
13
14
22
21
20
19
18
17
16
15
SDATA
SCLK
IA(0:2)
S(0,1)
I
2
C
Control
Logic
Note:
1. XIN is the frequency of the clock on the device鈥檚 XIN pin.
Cypress Semiconductor Corporation
Document #: 38-07034 Rev. *D
鈥?/div>
3901 North First Street
鈥?/div>
San Jose, CA 95134
鈥?/div>
408-943-2600
Revised May 12, 2003

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