Enable/Disable control of indi-
vidual DMA requests
C8237
Programmable
DMA Controller
Altera Core
Four, independent DMA chan-
nels
Independent auto-initialization of
all channels
Memory-to-Memory transfers
Memory block initialization
Address increment of decrement
Directly expandable to any
number of channels
The C8237 Programmable DMA Controller core (C8237 core) is a peripheral inter-
face circuit for microprocessor systems. The core is designed for use with an
external, 8-bit address latch. It contains four independent channels and may be ex-
panded to any number or channels by cascading additional controller chips. Each
channel has a full 64K address and word count capability.
End of process input for termi-
nating transfers
Software DMA requests
Independent polarity control for
DREQ and DACK signals
The C8237 was developed in
HDL and synthesizes to ap-
proximately 5,500 gates
depending on the technology
used.
Functionality based on the Intel
8237
Applications
The C8237 core is designed to improve system performance by allowing external
devices to directly transfer information from the system memory.
Block Diagram
RESET
CLK
CSN
READY
IORNIN
IOWNIN
EOPNIN
AEN
ADSTB
EOPNOUT
MEMRN
MEMWN
IORNOUT
IOWNOUT
HLDA
16 Bit
Decrementor
Temp Word
Count Reg
Timing
and
Control
16 Bit
Incrementor/
Decrementor
Temp Address Reg
AOUT[7:0]
Channel-3
Channel-2
C8237REG
Channel-1
Channel-0
State
Machine
Read/Write
Current Word
Count Register
Write
Base Word Count
Register
Base Word Address
Register
Current Word
Address Register
DBOUT(7:0)
DREQ(3:0)
HRQ
DACK(3:0)
Fixed
Priority
and
Rotating
Priority
Logic
Command
Register
Mask
Register
Request
Register
Mode
Register
Status
Register
Temporary
Register
DBIN(7:0)
AIN[3:0]
March 2004
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