C8051F41x
2.0 V, 32/16 kB, smaRTClock, 12-Bit ADC MCU
Analog Peripherals
12-bit ADC
High-Speed 8051 CPU
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鹵1 LSB INL; no missing codes
Programmable Throughput up to 200 ksps
Up to 24 External Inputs; programmable as single-ended or differential
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (鹵3 擄C)
Internal Voltage Reference鈥?.5 V, 2.2 V (programmable)
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 50 MIPS throughput with 50 MHz system clock
Expanded interrupt handler
2304 bytes data RAM
16 kB, 32 kB Flash; in-system programmable in 512-Byte Sectors; Full
Read/Write/Erase Functionality at 2.25 V
DD
64 bytes battery-backed RAM
24 port I/O; up to 5.25 V tolerance
Hardware SMBus鈩?(I2C鈩?compatible), SPI鈩? and UART serial ports
available concurrently
16-bit programmable counter array with six capture/compare modules,
WDT
4 general-purpose 16-bit counter/timers
Internal Oscillators: 24.5 MHz, 2% Accuracy Supports UART Operation;
Clock Multiplier up to 50 MHz
External Oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
External smaRTClock Oscillator: 32 kHz Crystal or self
resonant oscillator
Fast wake up from suspend mode in <1 碌s
Can switch between clock sources on-the-fly
Memory
Two 12-Bit Current Mode DACs
Two Comparators
Programmable hysteresis values and response time
Configurable to generate interrupts or reset
Digital Peripherals
POR/Brown-out Detector
On-Chip Debug
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints
Inspect/modify memory, registers, and stack
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Built-in LDO regulator: 2.1 V or 2.5 V
Battery switchover circuit
Back-up power supply
Oscillator failure detect
Operates down to 1 V
Clock Sources
Supply Voltage: 2.0鈥?.25 V
smaRTClock鈩?/div>
Available in 28-Pin QFN and 32-Pin LQFP
Temperature Range: 鈥?0 to +85 擄C
VREGIN
VDD
VRTC-BACKUP
GND
VREG
(to rest of chip)
VIO
(to smarRTClock Block)
Port 0
Latch
Port 1
Latch
UART
C
R
O
S
S
B
A
R
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
IDAC0
Battery Switch-Over Circuit
(VDD >= VRTC-BACKUP)
C2D
P0.0/IDAC0
P0.1/IDAC1
P0.2
P0.3
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0/XTAL1
P1.1/XTAL2
P1.2/VREF
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7/C2D
Debug HW
Reset
/RST/C2CK
POR
Brown-
Out
8
0
5
1
x16
32 kB
FLASH
256 B
SRAM
2 kB
XRAM
Timer
0,1,2,3
PCA x6 /
WDT
SMBus
SPI
Port 2
Latch
12-bit
IDAC0
12-bit
IDAC1
XTAL1
XTAL2
External
Oscillator
Circuit
24.5 MHz
2% Oscillator
Clock
Mult.
C
o
SFR Bus
r
CRC
e
Engine
IDAC1
CP1
CP0
+
-
+
-
XTAL3
XTAL4
32 KHz
Oscillator
64B RAM
VREF
VDD
Temp
smaRTClock
State
Machine
smaRTClock Block
smaRTClock Alarm
12-bit
200 ksps
ADC
A
M
U
X
AIN0-AIN23
Small Form Factor
Copyright 漏 2006 by Silicon Laboratories
2.24.2006
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