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C8051F2XX Datasheet

  • C8051F2XX

  • Mixed Signal 8 kB ISP Flash MCU Family

  • 146頁

  • ETC

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C8051F2xx
Mixed Signal 8 kB ISP Flash MCU Family
Analog Peripherals
-
SAR ADC
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-
Two Comparators
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12-bit resolution ('F206)
8-bit resolution ('F220/1/6)
鹵1/4 LSB INL (8-bit) and 鹵2 LSB INL (12-bit)
Up to 100 ksps
Up to 32 channel input multiplexer; each port
I/O pin can be an ADC input
16 programmable hysteresis states
Configurable to generate interrupts or reset
Memory
-
256 bytes internal data RAM
-
1024 bytes XRAM (available on 'F206/226/236)
-
8 kB Flash; In-system programmable in 512 byte
sectors
-
V
DD
monitor and brown-out detector
On-Chip JTAG Debug
-
On-chip debug circuitry facilitates full speed,
-
-
-
-
non-intrusive in-system debug (No emulator
required)
Provides breakpoints, single-stepping, watchpoints,
stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Complete, low cost development kit
Digital Peripherals
-
Four byte wide Port I/O; All are 5 V tolerant
-
Hardware UART and SPI bus
-
3 general purpose 16-bit counter/timers
-
Dedicated watch-dog timer
-
Bi-directional reset
-
System clock: internal programmable oscillator,
external crystal, external RC, or external clock
Supply Voltage
2.7 to 3.6 V
-
Typical operating current: 10 mA @ 25 MHz
-
Multiple power saving sleep and shutdown modes
(48-Pin TQFP and 32-Pin LQFP Version
Available)
Temperature Range: 鈥?0 to +85 擄C
High Speed
-
8051 mC Core
-
Pipelined Instruction Architecture; Executes 70% of
-
-
Instructions in 1 or 2 System Clocks
Up to 25MIPS Throughput with 25MHz Clock
Expanded Interrupt Handler
ANALOG PERIPHERALS
AMUX
DIGITAL I/O
SPI Bus
UART
Timer 0
Digital MUX
PGA
SAR
+
-
+
-
Timer 1
VOLTAGE
COMPARATORS
Timer 2
HIGH-SPEED CONTROLLER CORE
8051 CPU
CLOCK
EMULATION
JTAG
(25MIPS)
CIRCUIT
CIRCUITRY
8K x 8
SANITY
1280 x 8
22 INTERRUPTS
SRAM
ISP FLASH
CONTROL
Rev. 1.6 3/05
Copyright 漏 2005 by Silicon Laboratories
Port 3
Port 2
Port 1
ADC
Port 0
C8051F2xx

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