C8051F221
ANALOG PERIPHERALS
8-bit, 22-Channel ADC
-
22 External Inputs (Each Port I/O can be configured
as an ADC Input on the Fly!)
-
鹵1/2LSB
INL
-
No Missing Codes
-
Programmable Throughput up to 100ksps
Two Comparators
-
Programmable Hysteresis
-
Configurable to Generate Interrupts or Reset
VDD Monitor
and
Brown-out Detector
ON-CHIP JTAG EMULATION
-
On-Chip Emulation Circuitry Facilitates Full Speed,
Non-Intrusive In-Circuit Emulation
-
Supports Breakpoints, Single Stepping,
Watchpoints
-
Inspect/Modify Memory and Registers
-
Superior Performance to Emulation Systems Using
ICE-Chips, Target Pods, and Sockets
-
$99 Development Kit (C8051F226DK)
SUPPLY VOLTAGE .................... 2.7V to 3.6V
-
Typical Operating Current: 9mA @ 25MHz
-
Multiple Power Saving Sleep and Shutdown Modes
Mixed-Signal 8KB ISP FLASH MCU
PRELIMINARY
8051-COMPATIBLE
碌
C Core
-
Pipelined Instruction Architecture; Executes 70%
of Instructions in 1 or 2 System Clocks
-
Up to
25MIPS
Throughput with 25MHz Clock
-
Expanded Interrupt Handler; Up to 22 Interrupt
Sources
MEMORY
-
256 Bytes Data RAM
-
8k Bytes FLASH; In-System Programmable in 512
byte Sectors
DIGITAL PERIPHERALS
-
22 Port I/O; All are 5V tolerant
TM
-
Hardware SPI and UART Serial Ports Available
Concurrently
-
Three 16-bit Counter/Timers
-
Dedicated Watch-Dog Timer
-
Bi-directional Reset
CLOCK SOURCES
-
Internal Programmable Oscillator: 2-to-16MHz
-
External Oscillator: Crystal, RC, C, or Clock
-
Can Switch Between Clock Sources on-the-fly;
Useful in Power Saving Modes
Temperature Range: 鈥?0擄 C to +85擄 C
擄
擄
32-Pin LQFP Package
SPI is a trademark of Motorola, Inc.
VDD
Analog/Digital
Power
Port I/O Mode
& Config.
Port 0
Latch
UART
Timer 0
Timer 1
Timer 2
P
0
D
r
v
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
GND
P
0
M
U
X
TCK
TMS
TDI
TDO
/RST
JTAG
Logic
Debug HW
Reset
VDD
Monitor
WDT
External
Oscillator
Circuit
Internal
Oscillator
8
0
5
1
Port 1
Latch
CP0+
CP0
CP0
8kbyte
FLASH
256 byte
SRAM
P
1
M
U
X
P
1
D
r
v
CP0-
CP1+
CP1-
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
CP1
CP1
XTAL1
XTAL2
System Clock
C
o
SFR Bus
r
e
Comparator
Config.
Port 2
Latch
SPI
Port Mux
Control
P
2
M
U
X
P
2
D
r
v
P
3
D
r
v
A
M
U
X
P2.0/NSS
P2.1/MISO
P2.2/MOSI
P2.3/SCK
P2.4
P2.5
Clock & Reset
Configuration
Port 3
Latch
ADC
Config. &
Control
VDD
VREF
8-bit
100ksps
ADC
AIN0-AIN21
VREF
12.20.2000
1
2
