C8051F065
25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
Two 16-Bit ADCs
High-Speed 8051 碌C Core
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鹵0.75 LSB INL; no missing codes
Programmable throughput up to 1 Msps (each ADC)
1 external input each; programmable as two single-ended or one differ-
ential ADC
DMA to XRAM or external memory interface
Data-dependent windowed interrupt generator
16 programmable hysteresis values
Configurable to generate interrupts or reset
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
4352 bytes data RAM
64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
24 port I/O; all are 5 V tolerant
Hardware SMBus鈩?(I2C鈩?compatible), SPI鈩? and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with six capture/compare mod-
ules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timers or PCA
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Typical operating current: 18 mA at 25 MHz
Multiple power saving sleep and shutdown modes
Memory
Three Comparators
Digital Peripherals
Internal Voltage Reference
Precision V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
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On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
Clock Sources
Supply Voltage: 2.7 to 3.6 V
64-Pin TQFP
Temperature Range: 鈥?0 to +85 擄C
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
Digital Power
Analog Power
TCK
TMS
TDI
TDO
RST
MONEN
XTAL1
XTAL2
JTAG
Logic
Boundary Scan
Debug HW
Reset
8
0
5
1
C
o
r
e
UART0
UART1
SMBus
SPI Bus
PCA
P0
Drv
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
VDD Monitor
External
Oscillator
Circuit
25 MHz 2%
Internal
Oscillator
WDT
SFR Bus
Timers 0,
1, 2,3,4
P0, P1,
P2, P3
Latches
C
R
O
S
S
B
A
R
P1
Drv
P2
Drv
P2.0
P2.7
System Clock
64 kB
FLASH
256 Byte
RAM
4 kB
RAM
CP1
CP2
P3
Drv
VREF
VREF
CP0
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P2.6
P2.7
P2.2
P2.3
P2.4
P2.5
AVDD
ADGND
AV+
AGND
VREF0
VRGND0
AIN0
AIN0G
VBGAP0
CNVSTR0
AVDD
ADGND
AV+
AGND
VREF1
VRGND1
AIN1
AIN1G
VBGAP1
CNVSTR1
ADC0
1 Msps
(16-Bit)
R
E
S
U
L
T
0
External Data
Memory Bus
P4 Latch
Ctrl Latch
P5 Latch
Addr15-8
P6 Latch
Addr7-0
P7 Latch
Data Latch
P4
DRV
P5
DRV
P6
DRV
P7
DRV
ADC1
1 Msps
(16-Bit)
R
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U
L
T
1
危
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D
I
F
F
DMA
EMIF
Cntrl
Precision Mixed Signal
Copyright 漏 2004 by Silicon Laboratories
7.28.04
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