C8051F046
25 MIPS, 32 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
Memory
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鹵1 LSB INL; guaranteed monotonic
Programmable throughput up to 100 ksps
13 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (鹵3 擄C)
60 V common mode input range
Offset adjust from 鈥?0 to +60 V
16 gain settings from 0.05 to 16
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4352 bytes data RAM
32 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
External parallel data memory interface
32 message objects
鈥滿ailbox" implementation only interrupts CPU when needed
64 port I/O; all are 5 V tolerant
Hardware SMBus鈩?(I2C鈩?compatible), SPI鈩? and two UART serial
ports available concurrently
Programmable 16-bit counter array with 6 capture/compare modules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timer 3 or PCA
Internal programmable 2% oscillator: up to 25 MHz
External oscillator: Crystal, RC, C, or Clock
Typical operating current: 10 mA at 25 MHz
Multiple power saving sleep and shutdown mode
CAN Bus 2.0B
Digital Peripherals
High-Voltage Differential Amplifier
Three Comparators
Internal Voltage Reference
Precision V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
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On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor, pro-
gram trace memory
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
Clock Sources
Supply Voltage: 2.7 to 3.6 V
100-Pin TQFP
Temperature Range: 鈥?0 to +85 擄C
High-Speed 8051 碌C Core
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AV+
AGND
AGND
AGND
TCK
TMS
TDI
TDO
RST
Digital Power
Analog Power
JTAG
Logic
Boundary Scan
Debug HW
Reset
8
0
5
1
C
o
r
e
UART0
UART1
P0
Drv
P0.0
P0.7
SFR Bus
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
32 kB
FLASH
32x136
CANRAM
256 byte
RAM
4 kB
XRAM
MONEN
VDD
Monitor
External
Oscillator
Circuit
VREF
Port
0,1,2,3
&4
Latches
C
R
O
S
S
B
A
R
P1
Drv
P1.0
P1.7
P2
Drv
P2.0/CPx
P2.7/CPx
P3
Drv
P3.0/AINAMUX0
P3.7/AINAMUX7
CANTX
CANRX
WDT
XTAL1
XTAL2
VREF
CAN
2.0B
System
Clock
Internal
2%
Oscillator
CP0
CP1
CP2
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P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
A
M
U
X
Prog
Gain
ADC
100 ksps
(10-Bit)
P4.0
External Data Memory Bus
Port 4 <from crossbar>
Bus Control
Address [15:0]
P4
DRV
Ctrl Latch
P5 Latch
Addr [7:0]
P6 Latch
Addr [15:8]
P7 Latch
P5
DRV
P6
DRV
P7
DRV
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A0
P5.7/A7
P6.0/A8
P6.7/A15
P7.0/D0
P7.7/D7
TEMP
SENSOR
HVAIN+
HVAMP
A
M
U
X
8:2
Data [7:0]
HVAIN-
HVREF
HVCAP
Data Latch
CAN 2.0B
Copyright 漏 2004 by Silicon Laboratories
10.11.2004
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