C8051F040
ANALOG PERIPHERALS
12-bit ADC
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鹵1LSB
INL; Guaranteed Monotonic
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Programmable Throughput up to 100ksps
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12 External Inputs; Programmable as Single-Ended or Differential
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Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
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Data Dependent Windowed Interrupt Generator
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Built-in Temperature Sensor (鹵 3擄C)
High-Voltage Differential Amplifier
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60V Common Mode Input Range
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Offset Adjust from 鈥?0V to +60V
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16 Gain Settings from 0.05 to 16
8-bit ADC
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Programmable Throughput up to 500ksps
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8 External Inputs; Programmable as Single-Ended or Differential
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Programmable Amplifier Gain: 4, 2, 1, 0.5
Two 12-bit DACs
Three Comparators
Internal Voltage Reference
Precision VDD Monitor/Brown-out Detector
CAN2.0B 64KB ISP FLASH MCU
PRELIMINARY
HIGH SPEED 8051
碌
C CORE
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Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1 or 2
System Clocks
Up to 25MIPS Throughput with 25MHz System Clock
Expanded Interrupt Handler
4352 Bytes Internal Data RAM (256 + 4k)
64k Bytes In-System Programmable FLASH Program Memory
External 64k Byte Data Memory Interface
32 Message Objects
鈥淢ailbox鈥?implementation only interrupts CPU when needed
64 Port I/O; All are 5V tolerant
Hardware SMBus
TM
(I2C
TM
Compatible), SPI
TM
, and
Two
UART Serial
Ports Available Concurrently
Programmable 16-bit Counter Array with 6 Capture/Compare Modules
Five General Purpose 16-bit Counter/Timers
Dedicated Watch-Dog Timer; Bi-directional Reset
Internal Programmable 2% Oscillator: Up to 25MHz
External Oscillator: Crystal, RC, C, or Clock
Real-Time Clock Mode using Timer 3 or PCA
Typical Operating Current: 10mA @ 25MHz
Multiple Power Saving Sleep and Shutdown Modes
MEMORY
CAN Bus 2.0B
DIGITAL PERIPHERALS
ON-CHIP JTAG DEBUG & BOUNDRY SCAN
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VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AV+
AGND
AGND
AGND
TCK
TMS
TDI
TDO
/RST
On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive In-
System Debug (No Emulator Required!)
Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor, Program Trace Memory
Inspect/Modify Memory and Registers
Superior Performance to Emulation Systems Using ICE-Chips,
Target Pods, and Sockets
IEEE1149.1 Compliant Boundary Scan
Digital Power
CLOCK SOURCES
SUPPLY VOLTAGE ......................... 2.7V to 3.6V
100-Pin TQFP; Temp Range 鈥?0擄C to +85擄C
擄
擄
UART0
UART1
P0
Drv
P0.0
P0.7
Analog Power
JTAG
Logic
Boundary Scan
Debug HW
Reset
8
0
5
1
C
o
r
e
SFR Bus
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
64K byte
FLASH
32x136
CANRAM
256 byte
RAM
4K byte
XRAM
MONEN
VDD
Monitor
External
Oscillator
Circuit
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
Port
0,1,2,3
&4
Latches
C
R
O
S
S
B
A
R
P1
Drv
P1.0/AIN1.0
P1.7/AIN1.7
P2
Drv
P2.0/CPx
P2.7/CPx
P3
Drv
P3.0/AIN0.6
P3.7/AIN0.7
CTX0
CRX0
WDT
XTAL1
XTAL2
VREF
VREFD
DAC1
CAN
2.0B
ADC
500KS/s
(8-Bit)
Prog
Gain
System
Clock
A
M
U
X
8:1
VREF2
CP0
CP1
CP2
Internal
2%
Oscillator
+
-
+
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+
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P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
A
M
U
X
Prog
Gain
ADC
100ksps
(12-Bit)
P4.0
Port 4 <from crossbar>
External Data Memory Bus
Bus Control
Address [15:0]
P4
DRV
Ctrl Latch
P5 Latch
Addr [7:0]
P6 Latch
Addr [15:8]
P7 Latch
P5
DRV
P6
DRV
P7
DRV
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A0
P5.7/A7
P6.0/A8
P6.7/A15
P7.0/D0
P7.7/D7
TEMP
SENSOR
A
M
U
X
HVAIN+
HVAMP
8:2
Data [7:0]
Data Latch
HVAIN-
HVREF
HVCAP
8.6.2002
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