C8051F019
ANALOG PERIPHERALS
16K Flash, 1.25K RAM, 10-Bit ADC, 48-Pin MCU
PRELIMINARY
10-bit ADC
-
鹵1LSB
INL; No Missing Codes
-
Programmable Throughput up to 100ksps
-
8 External Inputs; Differential or Single-Ended mode
-
Data Dependent Windowed Interrupt Generator
-
Built-in Temperature Sensor (鹵 3擄C)
Two Comparators
-
16 Programmable Hysteresis Values
-
Configurable to Generate Interrupts or Reset
Internal Voltage Reference
Precision VDD Monitor/Brown-out Detector
HIGH SPEED 8051
碌
C CORE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pipe-lined Instruction Architecture; Executes 70% of Instructions in 1
or 2 System Clocks
Up to 25MIPS Throughput with 25MHz System Clock
Expanded Interrupt Handler
1280 Bytes Internal Data RAM (256 + 1k)
16k Bytes In-System Programmable FLASH Program Memory
16 Port I/O; All are 5V tolerant
Hardware SMBus
TM
(I2C
TM
Compatible), SPI
TM
, and UART Serial
Ports Available Concurrently
Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
Four General Purpose 16-bit Counter/Timers
Dedicated Watch-Dog Timer; Bi-directional Reset
Internal Programmable Oscillator: 2-to-16MHz
External Oscillator: Crystal, RC, C, or Clock
Typical Operating Current: 12.5mA @ 25MHz
Multiple Power Saving Sleep and Shutdown Modes
MEMORY
DIGITAL PERIPHERALS
ON-CHIP JTAG DEBUG & BOUNDRY SCAN
-
-
-
-
-
-
On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive
In-System Debug (No Emulator Required!)
Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
Inspect/Modify Memory and Registers
Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
IEEE1149.1 Compliant Boundary Scan
Low Cost,
Complete
Development Kit
CLOCK SOURCES
SUPPLY VOLTAGE ....................................2.8V to 3.6V
48-Pin TQFP
Temperature Range: 鈥?0擄C to +85擄C
擄
擄
SMBus is a trademark of Intel Corp.; I2C is a trademark of Philips Semi.; SPI is a trademark of Motorola, Inc.
VDD
VDD
DGND
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
Digital Power
UART
SMBus
SPI Bus
Analog Power
5-Chnl
PCA
Boundary Scan
Debug HW
Reset
JTAG
Logic
VDD
Monitor
XTAL1
XTAL2
WDT
8
0
5
1
C
o
r
e
16kbyte
FLASH
256 byte
RAM
1024 byte
XRAM
Timers
0,1,2
Timer 3
Port 0
Latch
Port 1
Latch
Port 2
Latch
C
R
O
S
S
B
A
R
S
W
I
T
C
H
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
External
Oscillator
Circuit
Internal
Oscillator
System Clock
SFR Bus
Port 3
Latch
VREF
VREF
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
A
M
U
X
TEMP
SENSOR
ADC
100ksps
(10-Bit)
NC
NC
CP0
CP1
1.18.2002
1
2
