Product Brief
Freescale Semiconductor, Inc.
C-5e NETWORK PROCESSOR
Freescale Semiconductor, Inc...
FEATURES
鈥?Operating frequency of
266MHz with power
consumption of 9W at
1.2V typical
鈥?5Gbps of bandwidth for
nonblocking throughput
with over 4,500 MIPs of
computing power
鈥?17 programmable RISC
Cores for cell/packet
forwarding and 32
programmable Serial
Data Processors for
processing bit streams
鈥?On-chip classification
coprocessor supporting
over 46 million IPv4
lookups/second
鈥?Flexible interfaces
supporting virtually any
serial or parallel protocol
and individual port data
rate from DS1 to OC-48c/
STM-16
鈥?External C-Port traffic
manager for fine-grained
QoS
鈥?Simple and efficient
programming in
C-language with
robust APIs
鈥?Royalty-free reference
applications
鈥?Key alliances in fabrics,
coprocessors, network
software, and design
services
The
C-5e鈩?network processor (NP),
Motorola鈥檚
second generation network processor in the C-Port
family, is the most integrated, flexible, and functionally-
rich processor for developing and deploying advanced
services for next-generation networks. With its 5Gbps of
bandwidth and more than 4500 MIPs of computing
power, the C-5e NP more than satisfies the demanding
communications requirements for intelligent network
services, such as classification, traffic management, and
interworking functions.
The C-5e NP is compatible with Motorola鈥檚 Traffic Man-
agement Coprocessors (TMCs) to provide unprecedented
Quality of Service (QoS) capabilities. What鈥檚 more,
Motorola鈥檚 M-5鈩?Channel Adapter can extend the
C-5e NP鈥檚 data bandwidth reach to support full-duplex
OC-48c/STM-16 and channelized applications, enabling
high-speed network services.
The C-5e NP also integrates robust programming inter-
faces, a comprehensive development environment, and
third-party support from Motorola鈥檚 Smart Networks
Alliance to provide a platform approach that can simplify
and speed the development of full-featured networking
applications today, enable faster development within
and across product families, and provide a smooth migra-
tion path to future product generations.
SOFTWARE-OPTIMIZED NPU ARCHITECTURE
The C-5e NP was designed from the ground up to provide
a simple and robust programming model. It enables
complete programmability of forwarding plane tasks in
C-language using Applications Programming Interfaces
(APIs). To support this programming model, the
interactions among subsystems of the architecture are
very efficient with integrated coprocessor acceleration
for common tasks such as classification, traffic
management, buffer management, fabric interfacing,
and supervisory processing.
Traffic typically enters the C-5e NP through its 16
Channel Processors (CPs), each of which can
accommodate up to an OC-3鈥檚 worth of bandwidth. Each
CP contains a transmit and receive Serial Data Processor
(SDP), which operates like a VLIW engine, and a RISC
Core that is used for any application-specific purpose.
The SDPs control programmable external pin logic,
allowing them to implement a wide variety of Layer 1
interfaces including connection to T/E-Carrier framers,
10/100 Ethernet PHY (RMII), Gigabit Ethernet PHY (GMII
or TBI), OC-3/STM-1 PHY, OC-12/STM-4 PHY, and the
M-5 Channel Adapter, a Utopia 3/PoS PHY interface that
can support OC-48/OC-48c/STM-16 MPHY capabilities.
Ethernet MACs and SONET framers are embedded in the
SDP architecture.
At Layer 2, the SDPs can be independently configured to
support Ethernet, Packet over SONET (PoS), HDLC
streams, ATM, Frame Relay, FibreChannel, or virtually
any format, including MPLS and other encapsulations.
For More Information On This Product,
Go to: www.freescale.com
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