drain PMOS鈥?/div>
particularly cost
effective for
applications
with a low
digital gate
count
C20G Overview
聝
聝
聝
聝
Double poly, two metal layers
P-type epitaxy over p+ substrate
Allows the integration of 5V CMOS with high voltage
lateral DMOS and extended drain PMOS.
Particularly cost effective for applications with a low
digital gate count.
Features
聝
聝
聝
聝
聝
聝
聝
聝
聝
聝
聝
聝
5V mixed signal CMOS
Fully enhanced with 5V on the Gate
DMOS Blocking Voltages from 72V to >300V
High Voltage PMOS 72V to 300V
Isolated vertical NPN
High Value (10k/sq) and Low TCR poly
resistors
Low specific RON
Low mask count
Double resurf technique allows wide range of
breakdown voltage to be attained simply
through layout variation
BSIM3v3.22 models available in Spectre and
HSPICE format
Cadence Foundry Design Kit (FDK) available
Safe Operating Area characterised for high
voltage devices
Applications
聝
聝
聝
聝
聝
Information Technology
-
Ink jet printers
heads, Digital Mirror Displays, Computer
peripherals, Display drivers, Printer, Plotter
Biomedical
-
Electrokinetics, LOAC,
碌-Fluidics, Bio-particles Sorting, Drug
Delivery, Ultrasound imaging
Telecom
-
DWDM, VOAs, OADMs, OXCs,
Electro-optics, Mirrors, 碌-coils, RF amplifier,
Multiplexer, SLIC, Ring generator
Automotive
-
Most Applications : Speed,
Angles, Acceleration, Pressure, I-MEMS
Industrial
鈥?/div>
AC-DC converter, Relays, Linear
amplifier, Current regulator, HV generator
D M O S O n -Re sista n ce vs B re a kd o w n Voltag e
S p e c i f ic O n -R e s i s ta n c e ( m
鈩?c
m
2
)
1 0 00
100
10
1
0 .1
100
Analog Capabilities
聝
聝
聝
Double Poly Capacitor (C=0.75fF/sq 碌m)
Four types of poly resistors including high
value and low TCR
Isolated 10V vertical npn (尾 = 75)
C2 0G
Th e o r e tica l s ilico n
lim it
1 0 00
B V d ss (V )
Simplified Cross-Section of DMOS
B
S
G
p -to p
N -W e ll
D
n+
p -to p
G
27-Sep-02
03-70-00149-00
www.dalsasemi.com
p+
n+
p -ba se
p -e p ita xy
p -b a se
1
2
