C20F 2.0碌m 5/40V CMOS Process
C20F Overview
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Thick gate oxide
Double poly, two layer metal
P-type epitaxy over p+ substrate
Allows the integration of 5V CMOS with 40V CMOS
which can operate with 40V on both gate and drain.
Features
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Full integration of 5V and 40V mixed signal
CMOS on the same die
Single and double drain extensions on 40V
NMOS and 40V PMOS
40V double poly capacitor
High Value (10k:/sq) and Low TCR poly
resistor options
Mixed signal Cadence Foundry Design Kit
(FDK) available
Applications
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EL displays
CCD Drivers
Motor Control
Instrumentation
Telecom line cards
Layout Rules
Layer
Poly 1
Poly 2
Contact
Metal 1
Via
Metal 2
Width (碌m)
2
2
2x2
2.0
2.4 x 2.4
2.8
Space (碌m)
2.5
2
2
2.0
2.0
2.4
Mixed Signal Capabilities
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40V double poly capacitor (0.48fF/碌m虜)
High value poly resistor option (10k:/sq)
5V 2碌m CMOS
40V CMOS Propogation delay:-1.15nS/stage
for single extended
2.0nS/stage for double extended
Simplified Cross-Section of 40V CMOS
B
p+
40V N XF
G
S
n+
n -exte n d ed
40V PXF
D
n+
n -exte n d ed
p -e p ita xy
B
n+
S
G
D
p+
p+
p -exten d e d
p -exten d e d
n -w e ll
p -e p ita xy
26-Sep-02
03-70-00148-00
www.dalsa.com
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