. Low leakage process
鈥?/div>
Standard cell library available
Metal III pitch (width/space)
Poly pitch (width/space)
Contact
Via 1 & 2
Gate geometry
N-well junction depth
P-well junction depth
N+ junction depth
P+ junction depth
Gate oxide thickness
Inter poly oxide thickness
Description
The
1.2碌m
process provides flexibility,
speed and packing density needed in mixed signal
designs. The aggressive design rules on both metal
layers are comparable to most 0.8碌m processes.
Also, the overall design rules are compatible with
most other 1.2um processes making second
sourcing easy.
MOSFET Electrical Parameters
1.2 MICRON - 5 volts
Technology outline
鈥?/div>
Drain Engineered Structure to Ensure
Reliability against Hot-Carrier Injection
鈥?/div>
Planarization with non-etch-back
SOG Processes
鈥?/div>
State-of-the-art Metal technology :
Ti/TiN/Al/TiN sandwich
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Plasma Silicon Nitride Passivation
for Reliability against Moisture
鈥?/div>
Latchup Free Process on Non-Epi
Material Achieved
Vt (10x1.2碌m)
Ids (10x1.2碌m)
Gain
尾
(10x10碌m)
Body Factor (50x50碌m)
Bvdss
Subthreshold Slope
Maximum Substrate
Current (50x1.2碌m)
Field Threshold
L Effective
N Channel
P Channel
min. typ. max. min. typ. max.
0.55
0.70
220
73
0.56
10
15
90
0.20
10
15
1.0
10
10
0.85
0.55
0.70
115
24
0.73
12
90
.01
15
0.82
0.85
Units
Conditions
V
碌A/碌m
碌A/V
2
鈭歷
V
mV/dec.
碌A/碌m
V
碌m
saturation
Vds=Vgs=5v
Ids=20nA
Vds=0.1v
Vds=5.5v
Vgs=2.7v
Ids = 14碌A
L drawn =
1.5碌m
www.dalsasemi.com
For More Information:
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18 Boulevard de l鈥橝茅roport
Bromont, Qu茅bec, Canada
J2L 1S7
Tel :
Fax
email:
(450) 534-2321 ext. 1448
(800) 718-9701
(450) 534-3201
dalsasales@dalsasemi.com
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