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BW4104X Datasheet

  • BW4104X

  • BW4104X LVDS Receiver|Data Sheet

  • 7頁(yè)

  • ETC

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LVDS Receiver
BW4104X
DECEMBER 1998. Ver1.0
General Description
The BW4104X receiver converts the LVDS data
streams
back into 28bits of CMOS/TTL data. At a transmit clock
frequency of 65MHz, 24 bits of RGB data and 4bits of
LCD timing data and control data are transmitted at a
rate of 455Mbps per LVDS data channel. Using a
65MHz clock the throughput is 227Mbytes/sec. Devices
are offered with falling edge clocks for convenient
interface with a varity of graphics and LCD panel
controllers. This receiver is an ideal means to solve
EMI and cable size problems associated with wide high
speed TTL
interfaces.
Features
鈥?/div>
20 to 65MHz shift clock support
鈥?/div>
28:4 Data Channel Compression at up to
455Megabits/sec on each LVDS channel
鈥?/div>
Single 3.3V supply
鈥?/div>
Low Power CMOS Design
鈥?/div>
Power-down mode
鈥?/div>
Single pixel per clock XGA(1024x768) ready
鈥?/div>
Supports VGA,SVGA,XGA and higher
addressability
鈥?/div>
Up to 227 Megabytes/sec bandwidth
鈥?/div>
Narrow bus reduces cable size and cost
鈥?/div>
PLL requires no external components
鈥?/div>
Low profile 56 lead TSSOP package
鈥?/div>
Falling edge data strobe Receiver
Block Diagram
LVDS input buffer
RAN
Serial/Parallel
Data transfer
For channel A
outbuffer x 7
RXOUT<0:6>
RAP
RBN
For channel B
RBP
RCN
RCP
RDN
For channel D
RDP
outbuffer x 7
RXOUT<21:27>
For channel C
outbuffer x 7
RXOUT<14:20>
outbuffer x 7
RXOUT<7:13>
RCLKN
PLL
RCLKP
CLKOUT
PDWNN
Figure1 . LVDS Block Diagram
1 / 7

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    BW4104X LVDS Receiver|Data Sheet
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