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BW2010P Datasheet

  • BW2010P

  • BW2010P 25MHz ~ 250MHz FSPLL BW2010P|Data Sheet

  • 11頁

  • ETC

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25MHz ~ 250MHz FSPLL
General Description
The BW2010P is a Phase-Locked Loop (PLL) frequency
synthesizer constructed in CMOS process technology.
The PLL macrofunctions provide frequency multiplication
capabilities.The output clock frequency, Fout, is related to the
reference input clock frequency, Fin, by the following equation:
Fout = ( m*Fin ) / ( p*s )
where Fout is the output clock frequency.
Fin is the reference input clock frequency. m,p and s are the
values for programmable dividers. BW2010P consists of a
Phase/Frequency Detector(PFD), a Charge Pump an External
Loop Filter, a Voltage Controlled Oscillator(VCO), a 6bit
Pre-divider, an 8bit Main divider and 2bit Post Scaler as shown
in Figure 1.
BW2010P
FEB. 2000. Ver1.2.21
Features
- 0.35um CMOS process technology
- 3.3 Volt Single power supply
- Output frequency range: 25~ 250 MHz
- Jitter: 鹵100ps
- Output Duty ratio: 40% to 60%
- Input Duty ratio: 40% to 60%
- Frequency changed by programmable divider
- Power down mode
FUNCTIONAL BLOCK DIAGRAM
FIN
Pre Divider
P
PFD
Charge
Pump
Loop Filter
(External)
VCO
Post Scaler
Fout
S
Main Divider
M
Figure 1. FUNCTIONAL BLOCK DIAGRAM
SAMSUNG ELECTRONICS Co. LTD

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