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Frequency Doubler

BW2010AGP

DECEMBER 1998. Ver1.0

General Description

IN A.G.P.-2X Mode, the PLL output Frequency is

133

/

3

Mhz which is doubled with 66

/

3

Mhz Input

Frequency.

The PLL produces a good clock duty cycle with the

voltage controlled oscillator (VCO) running at

266

2

/

3

MHz and divide by 2.

The 133

1

/

3

MHz clock also has to be routed to all

outputs of the interface and proper care needs to be

taken such that the clock skew across the

interface is minimized.

* 66

2

/

3

= 66.66MHz

133

1

/

3

= 133.33MHz

266

2

/

3

= 266.66MHz

1

2

Features

. 0.35u CMOS device technology

. Single power supply : +3.3V

. Output frequency : 133

1

/

3

MHz

. Jitter : +/- 100ps

. Duty ratio : 49% to 51%

. Provision for 66

2

/

3

MHz Input frequency.

. Power Down mode

Functional Block

Diagram

VDD

VSS

VBB

FOUT

FOUT2X

Buffer

1/2

Buffer

1/2

PFD

FIN

Charge

Pump

VCO

Loop

Filter

FILTER

External

PWRDN

VDDA

VSSA

VSUB

Figure1 . Functional Block Diagram

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