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BUK563-48C Datasheet

  • BUK563-48C

  • PowerMOS transistor Voltage clamped logic level FET

  • 8頁

  • PHILIPS

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Philips Semiconductors
Product specification
PowerMOS transistor
Voltage clamped logic level FET
GENERAL DESCRIPTION
Protected N-channel enhancement
mode logic level field-effect power
transistor in a plastic envelope
suitable
for
surface
mount
applications.
The device is intended for use in
automotive applications. It has
built-in zener diodes providing active
drain voltage clamping.
BUK563-48C
QUICK REFERENCE DATA
SYMBOL
V
(CL)DSR
I
D
P
tot
T
j
W
DSRR
R
DS(ON)
PARAMETER
Drain-source clamp voltage
Drain current (DC)
Total power dissipation
Junction temperature
Repetitive clamped turn off
energy; T
j
= 150藲C
Drain-source on-state
resistance; V
GS
= 5 V
MIN.
40
TYP.
48
MAX. UNIT
58
21
75
175
50
85
V
A
W
藲C
mJ
m鈩?/div>
PINNING - SOT404
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DG
鹵V
GS
I
D
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Storage temperature
Junction temperature
CONDITIONS
continuous
continuous
-
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
-
-
MIN.
-
-
-
-
-
-
-
- 55
- 55
MAX.
30
30
15
21
15
84
75
175
175
UNIT
V
V
V
A
A
A
W
藲C
藲C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
CONDITIONS
with heatsink compound
minimum footprint,
FR4 board (see fig. 18)
MIN.
-
-
TYP.
-
50
MAX.
2
-
UNIT
K/W
K/W
February 1996
1
Rev 1.000

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