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BUK554-200B Datasheet

  • BUK554-200B

  • PowerMOS transistor Logic level FET

  • 7頁(yè)

  • PHILIPS

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Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
BUK554-200A/B
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
BUK554
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
V
GS
= 5 V
MAX.
-200A
200
9.2
90
175
0.4
MAX.
-200B
200
8.2
90
175
0.5
UNIT
V
A
W
藲C
鈩?/div>
PINNING - TO220AB
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
1 23
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
鹵V
GS
鹵V
GSM
I
D
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
CONDITIONS
-
R
GS
= 20 k鈩?/div>
-
t
p
鈮?/div>
50
碌s
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
-
-
MIN.
-
-
-
-
-
-
-
-
- 55
-
-200A
9.2
6.5
36
90
175
175
MAX.
200
200
15
20
-200B
8.2
5.8
33
UNIT
V
V
V
V
A
A
A
W
藲C
藲C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MIN.
-
-
TYP.
-
60
MAX.
1.67
-
UNIT
K/W
K/W
April 1993
1
Rev 1.100

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