Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal
cycling
performance.
Intended for use in Switched Mode
Power Supplies (SMPS) and general
purpose switching applications.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
200
2.0
8.3
0.9
UNIT
V
A
W
鈩?/div>
PINNING - SOT223
PIN
1
2
3
4
gate
drain
source
drain (tab)
DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g
1
2
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DS
V
DGR
鹵V
GS
I
D
I
DM
I
DR
I
DRM
P
tot
T
stg
T
j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
CONDITIONS
R
GS
= 20 k鈩?/div>
T
sp
= 25 藲C
T
sp
= 100 藲C
T
sp
= 25 藲C
T
sp
= 25 藲C
T
sp
= 25 藲C
T
sp
= 25 藲C
MIN.
-
-
-
-
-
-
-
-
-
-55
-
MAX.
200
200
30
2.0
1.3
8.0
2.0
8.0
8.3
150
150
UNIT
V
V
V
A
A
A
A
A
W
藲C
藲C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
CONDITIONS
MIN.
MAX.
UNIT
Drain-source non-repetitive I
D
= 2 A ; V
DD
鈮?/div>
50 V ; V
GS
= 10 V ;
unclamped inductive turn-off R
GS
= 50
鈩?/div>
energy
T
j
= 25藲C prior to surge
T
j
= 100藲C prior to surge
-
-
50
8
mJ
mJ
January 1998
1
Rev 1.000
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