Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BUJ105AB
GENERAL DESCRIPTION
High-voltage, high-speed planar-passivated npn power switching transistor in SOT404 (D
2
-PAK) surface-mount
package intended for use in high frequency electronic lighting ballast applications, converters, inverters, switching
regulators, motor control systems, etc.
QUICK REFERENCE DATA
SYMBOL
V
CESM
V
CBO
V
CEO
I
C
I
CM
P
tot
V
CEsat
h
FEsat
t
f
PARAMETER
Collector-emitter voltage peak value
Collector-Base voltage (open emitter)
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Total power dissipation
Collector-emitter saturation voltage
Fall time
CONDITIONS
V
BE
= 0 V
TYP.
-
-
-
-
-
-
0.3
11
20
MAX.
700
700
400
8
16
125
1.0
15
50
UNIT
V
V
V
A
A
W
V
ns
T
mb
鈮?/div>
25 藲C
I
C
= 4.0 A;I
B
= 0.8 A
I
C
= 4.0 A; V
CE
= 5 V
I
C
= 5 A; I
B1
= 1 A
PINNING - SOT404
PIN
1
2
3
mb
base
collector
emitter
collector
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
c
b
2
1
3
e
LIMITING VALUES8
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V
CESM
V
CEO
V
CBO
I
C
I
CM
I
B
I
BM
P
tot
T
stg
T
j
PARAMETER
Collector to emitter voltage
Collector to emitter voltage (open base)
Collector to base voltage (open emitter)
Collector current (DC)
Collector current peak value
Base current (DC)
Base current peak value
Total power dissipation
Storage temperature
Junction temperature
CONDITIONS
V
BE
= 0 V
MIN.
-
-
-
-
-
-
-
-
-65
-
MAX.
700
400
700
8
16
4
8
125
150
150
UNIT
V
V
V
A
A
A
A
W
藲C
藲C
T
mb
鈮?/div>
25 藲C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to mounting
base
Thermal resistance junction to ambient
minimum footprint, FR4 board
CONDITIONS
TYP.
-
55
MAX.
1.0
-
UNIT
K/W
K/W
October 2001
1
Rev 1.000
1
2
3
4
5
6
7
