Standard ICs
Quad D latch
BU4042B
The BU4042B is a four-circuit D latch with a common clock line and separate data input terminals.
When the polarity input is set to 鈥淗鈥? input (D) is presented to output (Q) as is, as long as the clock input is rising, and
when the clock input falls, output (Q) holds input (D) at that point. While the clock input is falling, output (Q) does not
change even if input (D) changes.
Also, if the polarity input is set to 鈥淟鈥? input (D) is presented to output (Q) as is, as long as the clock input is at 鈥淟鈥?/div>
level, and when the clock input goes to 鈥淗鈥?level, latching takes place.
鈥?/div>
Features dissipation.
1) Low power
2) Wide range of operating power supply voltages.
3) High input impedance.
4) High fan-out.
5) Direct drive of 2 L-TTL inputs and 1LS-TTL input.
鈥?/div>
Block diagram
Q
4
1
16 V
DD
Q
1
2
CL D
Q Q
Q
1
3
CL D
D
1
4
Q Q
13 D
3
14 D
4
15 Q
4
鈥?/div>
Logic circuit diagram
D
1
(4)
LATCH
1
(2)
(3)
Q
1
Q
1
D
2
(7)
LATCH
2
(10) Q
2
(9)
Q
2
D
3
(13)
LATCH
3
(11) Q
3
(12) Q
3
CLOCK
5
CL D
Q Q
12 Q
3
D
4
(14)
CLOCK
(5)
POLARITY
(6)
LATCH
4
POLARITY
6
CL D
11 Q
3
(1)
Q
4
(15) Q
4
D
2
7
Q Q
10 Q
2
V
SS
8
9
Q
2
鈥?/div>
Truth table
CLOCK
L
H
H
L
POLARITY
L
L
H
H
Q
D
LATCH
D
LATCH
1
BU4042B相關型號PDF文件下載
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