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BU38803 Datasheet

  • BU38803

  • System control servo

  • 7頁

  • ROHM

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Video ICs
System control servo
BU38603 / BU38703 / BU38803
The BU38603, BU38703 and BU38803 are servo controller ICs for VCRs. They contain a high-speed, 8-bit CPU and
perform the processing required for the drum, capstan, FV and PV completely in software, allowing a large reduction
in the number of external components required. They also contain high-performance linear amplifiers, eliminating the
need for interface ICs. Specialized hardware is included for items that require high-speed processing, to allow
efficient utilization of the CPU.
鈥?/div>
Applications camcorders
VHS VCRs and
鈥?/div>
Features
1) CPU
499 commands (69 types)
Memory-mapped I / O
Minimum command execution time: 250ns (8MHz)
2)ROM capacity
BU38603: 16384
脳
8 bit
BU38703: 24576
脳
8 bit
BU38803: 32768
脳
8 bit
3) RAM capacity: 512
脳
8bit
4) Interrupt
Pattern generator: 1
Watch-dog timer: 1
External interrupts: 1
FG interrupts: 5
Internal interrupts: 7
Two timers, serial transmission, interrupt, VHSW,
CTL interval timer (fixed) / VISS
鈭?/div>
Multi-layer interrupts possible.
5) Free-running counter: 19 bit
6) PWM output: 12 bit
脳
2
7) Pattern generator
17 bits from FRC MSB used.
Output
Internal: 3 bit
External (PO): 5 bit
External (PIO): 6 bit
8) Programmable pre-scaler
CFG: 7 bit
CTL: 6 bit
9) Head amplifier / chroma rotary
Generated from pattern generator output.
10) Built-in AGC. Five-bits used to switch the gain
control registers for the CTL amplifier.
11) CTL counter: 1 / 30 or 1 / 25
12) Data shift PLL calculation: 24 bit
13) Timer: 8 bit
脳
2
14) Synchronous serial input/output: 8 bit
脳
1
15) VH PULSE
V separeted from composite synchronous snal.
Pseudo V generated from pattern generator
output.
Superimposed pseudo H synchronized with
the composite synchronous signal.
16) VISS / VASS
VASS 0 / 1 discrimination
VISS discrimination threshold: 3
Aspect discrimination.
D / A CTL switching.
17) Standard I / O
Parallel I / O (PIO): 32 bit
Parallel output (PO): 6 bit
18) A / D converter: 8 bits
脳
8 channels
Can be masked-programmed to be parallel inputs.
19) Watch-dog timer
Setting period: 4
20) Linear circuits
DFG: amplifier / comparator
CFG: amplifier / comparator
CTL: differential amplifier / comparator
DPG: comparator
1

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