BU-65178 /65179*/61588 /61688*/61689*
MINIATURE ADVANCED COMMUNICATION ENGINE
eet
(MINI-ACE) and MINI-ACE PLUS*
tash e
a
id
ED
DESCRIPTION
u
AC
鈥檚 G
er to E User info.
Ref AC
nal
and additio
for
FEATURES
The BU-61588 Mini-ACE and
BU-61688 Mini-ACE Plus* integrates
two 5-volt-only transceivers, protocol,
memory management, processor
interface logic, and 4K x 16, or 64K x
16* words of RAM in a choice of pin
grid array (PGA), quad flat pack or gull
lead packages. The Mini-ACE is pack-
aged in a 1.0 square inch, low profile,
cofired ceramic multi-chip-module
(MCM) package making it the smallest
integrated MIL-STD-1553 BC/RT/MT
in the industry.
The Mini-ACE provides full compatibil-
ity to DDC鈥檚 BU-61580 and BU-65170
Advanced Communication Engine
(ACE). As such, the Mini-ACE includes
all the hardware and software archi-
tectural features of the ACE.
The Mini-ACE contains internal
address latches and bidirectional data
buffers to provide a direct interface to
a host processor bus.
The memory management scheme for
RT mode provides three data struc-
tures for buffering data. These struc-
tures, combined with the Mini-ACE鈥檚
extensive interrupt capability, serve to
ensure data consistency while off-
loading the host processor.
The Mini-ACE Plus* can optionally
boot-up as a RT with the Busy bit set
for 1760 applications.
The Mini-ACE BC mode implements
several features aimed at providing an
efficient real-time software interface to
the host processor including automatic
retries, programmable intermessage
gap times, automatic frame repetition,
and flexible interrupt generation.
The advanced architectural features of
the Mini-ACE, combined with its small
size and high reliability, make it an ideal
choice for demanding military and indus-
trial processor-to-1553 applications.
鈥?/div>
5 Volt Only
鈥?/div>
Fully Integrated
MIL-STD-1553 A/B
STANAG 3838 Compliant Terminals
鈥?/div>
One-Square-Inch Package
鈥?/div>
Smallest BC/RT/MT In The Industry
鈥?/div>
Hardware and Software Compatible
with BU-61580 ACE Series
鈥?/div>
Flexible Processor/Memory Interface
鈥?/div>
Bootable RT* Option
鈥?/div>
4K x 16 or 64K x 16* Shared RAM
鈥?/div>
Automatic BC Retries
鈥?/div>
Programmable BC Gap Times
鈥?/div>
Programmable Illegalization
鈥?/div>
Simultaneous RT/Monitor Mode
鈥?/div>
Operates From 10*/12 /16 / 20* MHz Clock
TX/RX_A
4K X 16
OR
64K X 16
SHARED
RAM
TRANSCEIVER
A
*
CH. A
TX/RX_A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
DATA
BUFFERS
D15-D0
PROCESSOR
DATA BUS
TX/RX_B
ADDRESS BUS
ADDRESS
BUFFERS
A15-A0
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
TX/RX_B
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RT ADDRESS
RT_AD_LAT
RTAD4-RTAD0, RTADP
MISCELLANEOUS
CLK_IN,
MSTCLR,SSFLAG/EXT_TRG
FIGURE 1. BU-65178 / 65179* /61588 /61688*/61689* BLOCK DIAGRAM
漏
1996, 1999 Data Device Corporation
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